FPGA Verification Architect for First-Pass Silicon

Altera; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang is seeking an FPGA Silicon Design Verification Engineer to join our hardware team. You will lead pre-silicon verification of FPGA IP blocks, subsystems, and SoC designs, using SystemVerilog/UVM, ABV, and coverage-driven methodologies.

You will build and maintain verification environments, write constrained-random tests, and develop SVAs. Collaboration with RTL, architecture, and firmware teams is essential for first-pass silicon success and tape-out readiness.

Qualifications

• Requires a degree in Electrical/Computer Engineering or related field.
• 3+ years of digital design verification experience for FPGA/ASIC.
• Proficiency in SystemVerilog, UVM, ABV and constrained-random verification.

Responsibilities

• Develop and execute verification plans based on architecture and design specs.
• Build reusable SystemVerilog/UVM testbenches, sequences and scoreboards.
• Create directed and constrained-random tests to verify FPGA designs.
• Define verification metrics: functional, code and assertion coverage.
• Develop SystemVerilog Assertions to validate design behavior.
• Debug and perform root-cause analysis using simulation and waveform data.
• Collaborate with RTL, architecture and firmware teams to resolve issues.
• Support verification closure and sign-off prior to tape-out or FPGA release.

Skills

SystemVerilog

UVM

SVA

Functional Coverage

Python

Git

Constrained-random

Diagnostics & Debugging

Education

Bachelor’s or Master’s in Electrical Engineering / Computer Engineering / Computer Science

Tools

Synopsys VCS

Cadence Xcelium

QuestaSim

Job description

Altera in Penang is seeking an FPGA Silicon Design Verification Engineer to join our hardware team. You will lead pre-silicon verification of FPGA IP blocks, subsystems, and SoC designs, using SystemVerilog/UVM, ABV, and coverage-driven methodologies.

You will build and maintain verification environments, write constrained-random tests, and develop SVAs. Collaboration with RTL, architecture, and firmware teams is essential for first-pass silicon success and tape-out readiness.