Physical Design | STA Engineer

UST Malaysia; Penang; Sur place; MYR 180 000 - 260 000; Plein temps

Résumé du poste

UST Malaysia seeks an experienced ASIC physical design engineer to drive full-chip and block-level implementation, from floorplanning to routing and CTS. You will close timing across MCMM and ensure PPA goals while validating with STA using PrimeTime.

Collaboration with front-end and power teams is essential, along with scripting to streamline workflows. Experience with FinFET nodes (16/14/12nm) and PnR tools such as ICC2, Fusion Compiler, and Innovus is required.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• 4-8 years of ASIC physical design (PnR and STA focus).
• Strong hands-on experience with FinFETs and 16/14/12nm nodes.

Responsabilités

• Drive full-chip and block-level physical implementation: floor planning, placement, CTS, routing, optimization.
• Perform timing closure across MCMM conditions; ensure PPA goals.
• Conduct STA using PrimeTime or equivalent; implement timing ECOs and signoff.
• Perform DRC/LVS, crosstalk analysis, and EM/IR checks for reliability.
• Collaborate with front-end, STA, and power teams to resolve timing and design-rule issues.
• Develop scripts (Tcl, Perl, Python) to automate physical design and STA workflows.
• Utilize ICC2/ICC, Fusion Compiler, or Innovus for PnR implementation and optimization.
• Support tape-out activities and physical database management.

Connaissances

Tcl scripting

Perl scripting

Python scripting

Timing analysis

Clock tree synthesis

Physical design

P&R tools

Formation

Bachelor's or Master's in Electrical Engineering

Outils

Synopsys PrimeTime

Synopsys ICC2

Fusion Compiler

Cadence Innovus

Calibre

StarRC

Redhawk

Description du poste

Responsibilities

• Drive full-chip and block-level physical implementation, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization.
• Perform timing closure across multi-corner, multi-mode (MCMM) conditions, ensuring compliance with performance, power, and area (PPA) goals.
• Conduct static timing analysis (STA) using PrimeTime or equivalent tools, including timing ECO implementation and signoff validation.
• Perform physical verification (DRC/LVS), crosstalk analysis, and EM/IR checks to ensure design reliability and manufacturability.
• Collaborate with front-end design, STA, and power teams to resolve timing, congestion, and design rule issues efficiently.
• Develop and maintain methodology scripts (Tcl, Perl, or Python) to automate and streamline physical design and STA workflows.
• Utilize advanced PnR tools such as Synopsys ICC2/ICC, Fusion Compiler, or Cadence Innovus for implementation and optimization.
• Support tape-out activities, including design signoff and physical database management.

Requirements

• Bachelor’s or Master’s degree in Electrical/Electronic Engineering or a related field.
• At least 4-8 years of experience in ASIC physical design (PnR and STA focus).
• Strong hands-on experience with FinFET and advanced nodes (16nm, 14nm, 12nm, sub-10nm).
• Proficiency in timing analysis, optimization, and closure using Synopsys PrimeTime or equivalent.
• Experience in PNR implementation flows using Synopsys ICC2/Fusion Compiler, or Cadence Innovus.
• Solid understanding of design constraints (SDC), RC extraction, and timing ECOs.
• Knowledge of physical verification tools (Calibre, StarRC, Redhawk) is a plus.
• Proficient in scripting languages such as Tcl, Perl, and Python.
• Excellent analytical and problem-solving skills, with attention to detail and ability to work in a fast-paced environment.
• Willing to work in Bayan Lepas, Penang Malaysia.