Physical Design Engineer

Infinecs Systems Pvt. Ltd.; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

Infinecs Systems Pvt. Ltd. in Bayan Lepas (Penang) seeks a Physical Design Engineer to lead the RTL-to-GDS flow for cutting-edge SoC projects. You will perform synthesis, floorplanning, CTS, PnR, and signoff with a focus on power and timing accuracy.

The role requires hands-on experience with place-and-route, DRC/LVS, and advanced low-power methodologies, using Synopsys and Cadence tools. You will collaborate with global teams on tight schedules.

Qualifications

• Bachelor's degree in electrical/electronics/computer engineering or related discipline.
• Strong knowledge of digital logic, VHDL/RTL, and Verilog.
• Proficiency in Python, Perl, and TCL for CAD flow automation.
• Experience with Synopsys and Cadence EDA tools.
• Hands-on experience with place-and-route, CTS, timing convergence, and IR drop analysis.

Responsibilities

• Execute physical design flow from RTL to GDS (synthesis, floorplanning, power grid, PnR, CTS) and participate in design/architecture reviews.
• Evaluate and improve physical design methodologies for complex SoC/IP designs.
• Collaborate with local and multi-site teams, including remote members.
• Assist full-chip timing constraints development, STA, and timing signoff.
• Assist in full-chip physical verification (DRC/LVS) and EM/IR convergence.

Skills

Digital logic

VHDL/RTL

Verilog

CAD flow automation

Python scripting

Education

Bachelor's degree in Electrical Engineering

Electronics Engineering

Computer Engineering

Tools

Synopsys Fusion Compiler

PrimeTime

IC Validator

VC Low-Power

Innovus

Tempus

Virtuoso

Conformal Low-Power

Job description

# Physical Design EngineerBayan Lepas, Penang## Job DescriptionResponsibilities include (but are not limited to):● You will be participating in the leading-edge System-On-a-Chip (SoC) design projects using cuttingedge process technology nodes for various client applications.● Execute complete physical design flow from RTL to GDS (synthesis, floorplan, power grid, place and route, clock tree synthesis), participating in design/architecture reviews to track design milestones.● Evaluate and improve physical design methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules.● Actively work as part of a team both locally and with remote or multi-site teams.● Actively assists full chip timing constraints development, full chip Static Timing Analysis, andtiming signoff for a complex, multi-clock, multi-voltage SoC.● Actively assists in full chip physical verification activities including DRC and LVS convergence & EM/IR convergence## Requirements● Minimum of Bachelor’s degree in electrical engineering, Electronics Engineering, ComputerEngineering, or a related discipline.● Strong understanding of digital logic, VHDL/RTL representations, and Verilog.● Proficiency in Perl, TCL, and Python for CAD flow automation and optimization.● Experience with Synopsys EDA tools, including Fusion Compiler, PrimeTime, IC Validator, and VC Low‐Power.● Successful completion and/or tapeouts on advanced FinFET technology nodes (16nm, 12nm, 7nm, 5nm, 3nm), including low‐power design methodologies●Hands‐on experience with place‐and‐route (PnR) including floorplanning & clock tree synthesis (CTS), physical verification, timing convergence and IR drop analysis.● Experience in automated design flows and automated synthesis.Additional Skills:● Hands‐on experience with full‐chip or sub‐chip Static Timing Analysis, timing constraintdevelopment, and timing closure.● Experience with advanced sign‐off activities, including Lint, CDC, LEC, scan, and ECO flows.● Experience in top‐level physical implementation.● Experience with Cadence EDA tools, including Innovus, Tempus, Virtuoso, and ConformalLow‐Power.● Experience with power analysis and power optimization techniques.