Physical Design Engineer

Pride Global; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Pride Global in Malaysia is seeking an experienced Physical Design Engineer to lead end-to-end ASIC physical design from RTL to GDSII, with hands-on expertise in STA and timing closure.

The role requires 5+ years of ASIC PD experience, strong scripting in Tcl/Perl/Python, and collaboration with Front-End, DFT and verification teams on advanced nodes such as 7nm/5nm/3nm.

Qualifications

• 5+ years of experience in ASIC Physical Design.
• Hands-on experience with RTL-to-GDSII flow.
• Strong knowledge of STA, CTS, placement, routing and timing closure.
• Experience with advanced nodes such as 7nm/5nm/3nm preferred.
• Strong scripting skills in Tcl, Perl or Python.

Responsibilities

• End-to-end ASIC Physical Design from RTL to GDSII.
• Static Timing Analysis (STA) and timing closure.
• Setup/hold violation analysis and optimization.
• Physical Verification – DRC, LVS, ERC & Antenna.
• Power delivery, IR drop & signal integrity analysis.
• Collaborate with Front-End Design, DFT & Verification teams.

Skills

ASIC Physical Design

Physical Implementation

STA

RTL-to-GDSII

GDSII

Timing Closure

Scripting (Tcl/Python/Perl)

Power Integrity

Tools

Synopsys ICC2 / PrimeTime

Cadence Innovus / Tempus

Job description

We are looking for an experienced Physical Design Engineer with strong hands-on expertise in ASIC Physical Design / Physical Implementation to join our team in Malaysia.

• End-to-end ASIC Physical Design from RTL to GDSII
• Static Timing Analysis (STA) and Timing Closure
• Setup/Hold violation analysis and optimization
• Physical Verification – DRC, LVS, ERC & Antenna
• Power delivery, IR Drop & Signal Integrity analysis
• Collaborate with Front-End Design, DFT & Verification teams
• 5+ years of experience in ASIC Physical Design
• Strong understanding of RTL-to-GDSII implementation flow
• Hands-on experience with Synopsys ICC2 / PrimeTime or Cadence Innovus / Tempus
• Strong knowledge of STA, CTS, Placement, Routing & Timing Closure
• Experience with advanced nodes such as 7nm / 5nm / 3nm is preferred
• Strong scripting skills in Tcl, Perl or Python
• Strong analytical and troubleshooting skills

If you have strong ASIC Physical Design experience and are looking for an opportunity in Malaysia, we'd love to hear from you!

Interested candidates can DM me or share their updated CV at [e-mail]