Senior Physical Design & STA Engineer

UST Malaysia; Penang; On-site; MYR 180,000 - 260,000; Full time

Job summary

UST Malaysia seeks an experienced ASIC physical design engineer to drive full-chip and block-level implementation, from floorplanning to routing and CTS. You will close timing across MCMM and ensure PPA goals while validating with STA using PrimeTime.

Collaboration with front-end and power teams is essential, along with scripting to streamline workflows. Experience with FinFET nodes (16/14/12nm) and PnR tools such as ICC2, Fusion Compiler, and Innovus is required.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• 4-8 years of ASIC physical design (PnR and STA focus).
• Strong hands-on experience with FinFETs and 16/14/12nm nodes.

Responsibilities

• Drive full-chip and block-level physical implementation: floor planning, placement, CTS, routing, optimization.
• Perform timing closure across MCMM conditions; ensure PPA goals.
• Conduct STA using PrimeTime or equivalent; implement timing ECOs and signoff.
• Perform DRC/LVS, crosstalk analysis, and EM/IR checks for reliability.
• Collaborate with front-end, STA, and power teams to resolve timing and design-rule issues.
• Develop scripts (Tcl, Perl, Python) to automate physical design and STA workflows.
• Utilize ICC2/ICC, Fusion Compiler, or Innovus for PnR implementation and optimization.
• Support tape-out activities and physical database management.

Skills

Tcl scripting

Perl scripting

Python scripting

Timing analysis

Clock tree synthesis

Physical design

P&R tools

Education

Bachelor's or Master's in Electrical Engineering

Tools

Synopsys PrimeTime

Synopsys ICC2

Fusion Compiler

Cadence Innovus

Calibre

StarRC

Redhawk

Job description

UST Malaysia seeks an experienced ASIC physical design engineer to drive full-chip and block-level implementation, from floorplanning to routing and CTS. You will close timing across MCMM and ensure PPA goals while validating with STA using PrimeTime.

Collaboration with front-end and power teams is essential, along with scripting to streamline workflows. Experience with FinFET nodes (16/14/12nm) and PnR tools such as ICC2, Fusion Compiler, and Innovus is required.