Senior Physical Design Engineer

754 Altera Semiconductor Technology (M) Sdn. Bhd.; George Town; On-site; MYR 140,000 - 230,000; Full time

Job summary

754 Altera Semiconductor Technology (M) Sdn. Bhd. in Penang, Malaysia, seeks a Senior Physical Design Engineer to drive RTL-to-GDS design implementations for custom IP and SoC blocks.

You will lead the physical design flow, perform timing, power, and reliability analyses, and guide signoff across STA, LEC, ERC, and DRC checks. The role requires 5+ years in physical design with multiple tape-outs, hands-on HDL (VHDL/Verilog), and scripting (Perl/TCL/Python).

Qualifications

• 5+ years of relevant experience in physical design flow and EDA tools (Synthesis, PnR, STA).
• Hands-on expertise with scripting languages (Perl, TCL, Python) and HDL (VHDL/Verilog).
• Experience mentoring junior team members and charting their development.
• Strong initiative, analytical/problem-solving skills, and ability to work in a diverse team.

Responsibilities

• Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database ready for manufacturing.
• Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, STA, power distribution, and noise analysis.
• Conducts verification and signoff including formal equivalence verification, STA, reliability verification, LEC/ERC/DRC checks, and layout verification.
• Analyzes results and recommends fixes for current and future product architectures.
• Expertise in clock design, timing closure, power management, and DFT using industry standard EDA tools.

Skills

Mentoring

Analytical thinking

Team collaboration

Multitasking

Education

Bachelor's degree in computer engineering

Bachelor's degree in electronic engineering

Master's degree (preferred)

Tools

Perl

TCL

Python

VHDL

Verilog

Job description

Responsibilities

Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.

Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.

Analyzes results and makes recommendations to fix violations for current and future product architecture.

Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.

Optimizes design to improve product-level parameters such as power, frequency, and area.

Participates in the development and improvement of physical design methodologies and flow automation.

Qualifications

Education Requirements: Bachelor's degree in computer engineering, electronic engineering or related field.

• 5+ years of relevant experience in the following areas: multiple tape‑out experience in deep submicron process nodes, extensive knowledge and hands‑on experience in physical design flow and relevant EDA tools, extensive knowledge and hands‑on experience in physical design signoff flow (STA, LEC, ERC, DRC).


• Hands‑on expertise with scripting languages such as Perl, TCL, Python and knowledge of hardware description languages (VHDL, Verilog).


• Experience mentoring junior team members and charting their development for success.


• Strong initiative, analytical/problem‑solving skills, team‑working skills, ability to multitask and work within a diverse team environment.

Preferred Requirements

• Bachelor or master’s degree in computer engineering, electronic engineering or related field.


• 5+ years of experience in physical design involving multiple clock domains and clock, power management.


• Low power design, tools and methodologies.


• Power intent UPF specifications.

Job Type

Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.