Staff DDR Validation Engineer — LPDDR5X/LPDDR6 Bring-up

Qualcomm Incorporated; Tijuana; Sur place; MXN 420 000 - 650 000; Plein temps

Résumé du poste

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA seeks an experienced DDR Validation Engineer to lead end-to-end validation of LPDDR5X/LPDDR6 memory subsystems across AI Accelerator and flagship platforms. You will drive bring-up, training validation, and system-level debugging from pre- to post-silicon stages.

The role demands strong C/C++ development skills, post-silicon debugging proficiency, and collaboration with architecture, design, firmware, and DRAM vendors to ensure

Qualifications

• BS/MS/PhD in EE/CE/CS or related field with relevant experience.
• 4+ years in ASIC design/verification/validation (3+ or 2+ with advanced degrees).
• Strong knowledge of LPDDR4/5/5X/6 architectures, DDR controllers and PHYs, memory training and calibration.
• Understanding of cache, coherency, NoC, power management, and low-power memory features.

Responsabilités

• Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms.
• Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, and low-power state validation.
• Develop validation plans for memory functionality, performance, reliability, power, and corner cases.
• Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
• Validate DDR interactions with CPU, GPU, NPU, cache, NoC, and system software.
• Develop scalable automation, regression infrastructure, and debug analytics frameworks.
• Collaborate with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause issues.

Connaissances

DDR validation

Memory subsystem validation

C/C++

Post-silicon debug

Low-level software

Formation

Bachelor's degree in Science/Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Outils

DDR validation tools

Si/PI analysis tools

Description du poste

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA seeks an experienced DDR Validation Engineer to lead end-to-end validation of LPDDR5X/LPDDR6 memory subsystems across AI Accelerator and flagship platforms. You will drive bring-up, training validation, and system-level debugging from pre- to post-silicon stages.

The role demands strong C/C++ development skills, post-silicon debugging proficiency, and collaboration with architecture, design, firmware, and DRAM vendors to ensure