Senior DDR Validation Engineer for LPDDR5X/6 Bring-up

QUALCOMM, Inc.; Tijuana; On-site; MXN 500,000 - 750,000; Full time

Job summary

Qualcomm Semiconductor Baja California is seeking an experienced DDR Validation Engineer to lead end-to-end validation for LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and flagship mobile platforms. You will oversee memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

The role involves defining validation strategies across emulation, FPGA, and silicon, driving training, frequency scaling, and low-power state

Qualifications

• BS or MS or PhD in EE, CE, CS or related field.
• 5+ years of experience in DDR/memory subsystem validation or silicon bring-up.
• Proficiency in C/C++ and low-level software development.

Responsibilities

• Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms.
• Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement.
• Develop validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
• Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
• Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
• Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization.
• Develop scalable automation, regression infrastructure, and debug analytics frameworks.
• Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause issues.

Skills

C/C++

DDR memory validation

System validation

Education

BS/MS/PhD in EE/CE/CS

Tools

DDR controllers

DDR PHYs

Job description

Qualcomm Semiconductor Baja California is seeking an experienced DDR Validation Engineer to lead end-to-end validation for LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and flagship mobile platforms. You will oversee memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

The role involves defining validation strategies across emulation, FPGA, and silicon, driving training, frequency scaling, and low-power state