Senior DDR Validation Engineer – LPDDR5X/LPDDR6 Bring-up

Qualcomm

Tijuana

Sur place

MXN 850 000 - 1 200 000

Plein temps

Il y a 9 jours

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Résumé du poste

Qualcomm’s System Validation & Emulation (SVE) team seeks an experienced DDR Validation Engineer for end-to-end validation of LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms. This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

You will develop scalable validation plans, drive training validation, frequency scaling, low-power state validation, and feature

Qualifications

BS/MS/PhD in EE, CE, CS or related field with 4+ years in ASIC validation or memory bring-up.
Strong knowledge of LPDDR4/5/5X/6 architectures and DDR controllers/PHYs.
Experience with post-silicon debugging and system-level validation.
Proficiency in C/C++ and low-level software development.

Responsabilités

Define and execute DDR validation strategy across emulation, FPGA, and silicon.
Lead LPDDR5X/LPDDR6 bring-up, training, frequency scaling, and low-power state validation.
Develop validation plans for memory functionality, performance, reliability and power.
Debug DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
Validate interactions between DDR, CPU, GPU, NPU, cache, NoC and system software.
Develop automation, regression infrastructure, and debug analytics.
Collaborate with Architecture, Design, Firmware, SI/PI, and DRAM vendors.