DDR Validation Engineer, Staff

Qualcomm; Tijuana; On-site; MXN 850,000 - 1,200,000; Full time

Job summary

Qualcomm’s System Validation & Emulation (SVE) team seeks an experienced DDR Validation Engineer for end-to-end validation of LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms. This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

You will develop scalable validation plans, drive training validation, frequency scaling, low-power state validation, and feature

Qualifications

• BS/MS/PhD in EE, CE, CS or related field with 4+ years in ASIC validation or memory bring-up.
• Strong knowledge of LPDDR4/5/5X/6 architectures and DDR controllers/PHYs.
• Experience with post-silicon debugging and system-level validation.
• Proficiency in C/C++ and low-level software development.

Responsibilities

• Define and execute DDR validation strategy across emulation, FPGA, and silicon.
• Lead LPDDR5X/LPDDR6 bring-up, training, frequency scaling, and low-power state validation.
• Develop validation plans for memory functionality, performance, reliability and power.
• Debug DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
• Validate interactions between DDR, CPU, GPU, NPU, cache, NoC and system software.
• Develop automation, regression infrastructure, and debug analytics.
• Collaborate with Architecture, Design, Firmware, SI/PI, and DRAM vendors.

Skills

DDR validation

C/C++

Post-silicon debug

Memory subsystem

Education

Bachelor's degree in EE/CE/CS

Master's or PhD preferred

Job description

Company

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases.

This team focuses on content quality and system-level validation enablement, offering deep exposure to Qualcomm SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains.

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments, including:

• Premium mobile and flagship platforms
• Data center
• AI Accelerator platform

Role Overview

We are seeking an experienced DDR Validation Engineer for end-to-end validation of next-generation LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms. This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.

Key Responsibilities

• Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms.
• Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, low-power state validation, and feature enablement.
• Develop and execute validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
• Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
• Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
• Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization.
• Develop scalable automation, regression infrastructure, and debug analytics frameworks.
• Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause and resolve issues.

Minimum Requirements

• BS or MS or PhD in EE, CE, CS, or related field.
• 5+ years of experience in DDR/memory subsystem validation or silicon bring-up.
• Strong understanding of:
  • LPDDR4/5/5X/6 architectures
  • DDR controllers and PHYs
  • Memory training and calibration algorithms
  • Cache, coherency, and NoC architectures
  • Power management and low‑power memory features
• Strong post-silicon debug experience.
• Proficiency in C/C++ and low-level software development.

Preferred Qualifications

• Mobile SoC, AI compute, automotive, or server platform validation experience.
• Familiarity with SI/PI analysis, memory performance tuning, and thermal characterization.
• Experience driving first-silicon memory bring-up and volume production qualification.

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Applicants

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.