Senior DDR Validation Engineer: LPDDR5X/LPDDR6 Bring-Up

QUALCOMM, Inc.; Tijuana; On-site; MXN 420,000 - 700,000; Full time

Job summary

Qualcomm’s System Validation & Emulation (SVE) team seeks an experienced DDR Validation Engineer to validate LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and flagship mobile platforms, from pre-silicon through post-silicon.

You will lead bring-up, training validation, frequency scaling, and develop scalable automation and debug analytics while collaborating across Architecture, Design, Firmware, and DRAM vendors.

Qualifications

• BS/MS/PhD in EE, CE, CS, or related field.
• 5+ years of experience in DDR/memory subsystem validation or silicon bring-up.
• Strong understanding of LPDDR4/5/5X/6 architectures
• DDR controllers and PHYs
• Memory training and calibration algorithms
• Cache, coherency, and NoC architectures
• Power management and low-power memory features
• Strong post-silicon debug experience.
• Proficiency in C/C++ and low-level software development.

Responsibilities

• Define and execute DDR validation strategy across emulation, FPGA, and silicon platforms.
• Drive LPDDR5X/LPDDR6 bring-up, training validation, frequency scaling, and low-power state validation.
• Develop validation plans covering memory functionality, performance, reliability, power, and corner-case scenarios.
• Lead debug of DDR controller, PHY, firmware, SI/PI, timing, and system-level issues.
• Validate interactions between DDR, CPU, GPU, NPU, cache hierarchy, NoC, and system software.
• Drive bandwidth, latency, QoS, memory pressure, and AI workload characterization.
• Develop scalable automation, regression infrastructure, and debug analytics frameworks.
• Partner with Architecture, Design, Firmware, SI/PI, Package, and DRAM vendors to root-cause issues.

Skills

C/C++

Low-level software

Memory validation

ASIC knowledge

Education

BS/MS/PhD in EE/CE/CS

Job description

Qualcomm’s System Validation & Emulation (SVE) team seeks an experienced DDR Validation Engineer to validate LPDDR5X/LPDDR6 memory subsystems on AI Accelerator and flagship mobile platforms, from pre-silicon through post-silicon.

You will lead bring-up, training validation, frequency scaling, and develop scalable automation and debug analytics while collaborating across Architecture, Design, Firmware, and DRAM vendors.