HBM Layout Engineering Manager – Analog/Mixed-Signal Lead

Micron Technology; Región Centro; Vor Ort; MXN 1.000.000 - 1.400.000; Vollzeit

Zusammenfassung

Micron Technology in Guadalajara, Mexico, seeks a Layout Design Engineering Manager to lead a distributed team delivering analog, mixed-signal, and custom layouts for high-performance AI and HPC applications.

You will guide layout development, verification (DRC/LVS), and block-level delivery, while mentoring engineers and coordinating multiple projects across global teams. A strong CMOS background and hands-on IP experience are required.

Qualifikationen

• 15+ years of analog/custom layout design in advanced CMOS technologies.
• 5+ years of experience managing layout engineering teams.
• Expertise in layout verification and quality oversight.
• Bachelor’s/Master’s in Electronics or related field.

Aufgaben

• Manage a team responsible for crafting and developing critical layouts for analog circuits and mixed-signal components.
• Oversee layout verification activities including LVS, DRC, Antenna checks and documentation.
• Ensure timely delivery of block-level layouts meeting project requirements.
• Coordinate planning, scheduling, and execution for multiple projects and mentor engineers.
• Collaborate with global teams to align project goals across Micron’s footprint.

Kenntnisse

Analog/custom layout

Team management

Layout verification oversight

Tapeouts experience

Planar & FinFET CMOS

Cross-functional leadership

Ausbildung

Bachelor’s degree in Electronics/VLSI Engineering

Master’s degree in Electronics/VLSI or related field

Tools

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Tapeout tooling

Jobbeschreibung

Micron Technology in Guadalajara, Mexico, seeks a Layout Design Engineering Manager to lead a distributed team delivering analog, mixed-signal, and custom layouts for high-performance AI and HPC applications.

You will guide layout development, verification (DRC/LVS), and block-level delivery, while mentoring engineers and coordinating multiple projects across global teams. A strong CMOS background and hands-on IP experience are required.