HBM Layout Engineer for AI & HPC

Micron Technology, Inc.; Región Centro; Presencial; MXN 420 000 - 700 000; Tempo integral

Resumo da oferta

Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to join the HBM team. You will craft IC layouts for leaf, standard cells and sub-blocks, ensuring performance, power, area, and design efficiency while interpreting DRC/LVS results and collaborating with global teams.

You will work on pre-silicon and physical design challenges and contribute to AI-enabled methodologies for automation in high bandwidth memory projects.

Qualificações

• Bachelor/Master/PhD in Electronics, Mechatronics, Robotics or a related technical field.
• Graduation from a bachelor’s, master’s, or PhD program within the past two years.
• Strong understanding of electronic circuit concepts and proficiency in electronic circuit simulation or design tools.
• Conversational English proficiency and good interpersonal communication.

Responsabilidades

• Craft and develop IC layouts for leaf cells, standard cells, and sub-blocks with attention to performance, power, area, capacitance, and design efficiency.
• Interpret DRC/LVS and other physical verification results to support accurate layouts.
• Apply a systematic, detail-focused approach to problem-solving and physical verification while planning work efficiently.
• Collaborate with internal engineering teams across global locations to drive layout projects.
• Continue to learn and develop semiconductor design skills while contributing to innovative HBM solutions.

Conhecimentos

Layout design

Electronic circuit concepts

Circuit simulation/design tools

English communication

C++ or Python

AI-enabled methodologies

Formação académica

Bachelor/Master/PhD in Electronics/Mechatronics/Robotics or related field

Graduation within past 2 years

Ferramentas

Cadence VLE/VXL

Calibre DRC/LVS

Mentor Graphics

Descrição da oferta de emprego

Micron Technology, Inc. in Guadalajara, Mexico, is seeking a Layout Design Engineer to join the HBM team. You will craft IC layouts for leaf, standard cells and sub-blocks, ensuring performance, power, area, and design efficiency while interpreting DRC/LVS results and collaborating with global teams.

You will work on pre-silicon and physical design challenges and contribute to AI-enabled methodologies for automation in high bandwidth memory projects.