HBM Layout Design Lead — Analog/Mixed‑Signal Expert

Micron Technology; Región Centro; On-site; MXN 900,000 - 1,300,000; Full time

Job summary

Micron Technology, a world leader in memory and storage solutions, seeks a Layout Design engineer for the HBM Team in Guadalajara, Mexico. You will work on AI and HPC applications, collaborating with global teams across multiple projects to deliver high-quality layouts.

Ideal candidates have 5+ years of analog/custom layout experience, strong Cadence and Calibre skills, and a proven track record in delivering complex blocks such as PLLs and data converters within CMOS processes.

Qualifications

• 5+ years of experience in analog/custom layout design in advanced CMOS, Planar or FinFET.
• BE or MTech in Electronic/VLSI Engineering, or related.
• Expertise in Cadence VLE/VXL and Mentor Calibre DRC/LVS is a must.
• Experience creating layouts of critical blocks such as PLL, ADC, DAC, LDO, Bandgap, Ref Generators, etc.
• Knowledge of analog layout fundamentals and layout effects on speed, power and area.

Responsibilities

• Design and development of analog, mixed-signal, custom digital block and full chip level integration support.
• Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
• Responsible for on-time delivery of block-level layouts with acceptable quality.
• Lead planning, area/time estimation, scheduling, delegation and execution to meet project milestones across multiple projects.
• Communicate effectively with Global engineering teams to assure project success.

Skills

Analog layout design

Mixed-signal layout

Problem-solving

Global team communication

Project planning

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Calibre DRC/LVS

Job description

Micron Technology, a world leader in memory and storage solutions, seeks a Layout Design engineer for the HBM Team in Guadalajara, Mexico. You will work on AI and HPC applications, collaborating with global teams across multiple projects to deliver high-quality layouts.

Ideal candidates have 5+ years of analog/custom layout experience, strong Cadence and Calibre skills, and a proven track record in delivering complex blocks such as PLLs and data converters within CMOS processes.