EM/IR Closure Engineer, Physical Design Expert

Intel Corporation

Región Centro

Presencial

MXN 400.000 - 700.000

Jornada completa

Hace 6 días
Sé de los primeros/as/es en solicitar esta vacante

Recibe más respuestas de empleadores

Envía un currículum específico para el puesto de trabajo en cuestión de minutos.

Descripción de la vacante

Intel Corporation in Guadalajara, Mexico is seeking a hands-on Physical Design Engineer (EM/IR Closure) to own block-level reliability closure and drive EM/IR signoff within SAM frameworks, collaborating with Physical Design, STA and Methodology teams.

The role requires strong execution, knowledge of Python/Tcl/Perl scripting for design flows, experience with Calibre DRC and Synopsys/Cadence tools, and on-site work authorization in Mexico.

Formación

  • Bachelor's or BS degree in Electronics/Computer Engineering or related field with 3+ years experience.
  • OR Master's in Electronics/Computer Engineering or related field with 2+ years experience.
  • OR PhD in Electronics/Computer Engineering or related field with no experience.
  • Proficiency in scripting languages for design flow automation (Python/Tcl/Perl).
  • Experience with static timing analysis, layout verification tools (Calibre DRC), and physical clock design.
  • Experience in physical design for IP/SoC using Synopsys or Cadence tools.
  • Intermediate to advanced English; Mexican work authorization (no visa sponsorship).

Responsabilidades

  • Execute physical design implementation from RTL to GDS, including synthesis, P&R, STA, and floor planning.
  • Perform verification and signoff: formal verification, reliability checks, power integrity, layout checks, EDA timing analysis.
  • Identify violations and recommend architecture improvements.
  • Optimize designs to improve power, frequency, and area using standard EDA tools.
  • Develop physical design methodologies, automation flows, and processes.
  • Collaborate with cross-functional teams to meet Intel's quality and performance standards.

Conocimientos

Python
Tcl
Perl
English (intermediate)

Educación

Bachelor's or BS in Electronics Engineering, Computer Engineering, or related field
Master's in Electronics Engineering, Computer Engineering, or related specialized field
PhD in Electronics Engineering, Computer Engineering, or related specialized field

Herramientas

Synopsys tools
Cadence tools
Calibre DRC
PrimeTime PX
PrimeRail
Redhawk

Descripción del empleo

Intel Corporation in Guadalajara, Mexico is seeking a hands-on Physical Design Engineer (EM/IR Closure) to own block-level reliability closure and drive EM/IR signoff within SAM frameworks, collaborating with Physical Design, STA and Methodology teams.

The role requires strong execution, knowledge of Python/Tcl/Perl scripting for design flows, experience with Calibre DRC and Synopsys/Cadence tools, and on-site work authorization in Mexico.

Consigue la evaluación confidencial y gratuita de tu currículum.
o arrastra y suelta tu archivo aquí
Similar jobs

Puestos de trabajo similares que vale la pena comparar

Physical Design Engineer
Physical Design Engineer

Intel Corporation • Región Centro

Presencial
MXN 400.000 - 700.000
Physical Design Engineer
Physical Design Engineer

Intel • Región Centro

Híbrido
MXN 600.000 - 900.000
Hybrid Physical Design Engineer — RTL to GDS, Power/Area
Hybrid Physical Design Engineer — RTL to GDS, Power/Area

Intel • Región Centro

Híbrido
MXN 600.000 - 900.000
Sr Engineer, Memory CAD, Guadalajara
Sr Engineer, Memory CAD, Guadalajara

Micron Technology, Inc • Tlaquepaque

Presencial
MXN 1.387.000 - 1.909.000
DRAM IP Layout Engineer — Precision & Leadership
DRAM IP Layout Engineer — Precision & Leadership

Micron Technology • Tlaquepaque

Presencial
MXN 1.041.000 - 1.389.000
Sr Engineer/Layout Engineer, Memory CAD, Guadalajara
Sr Engineer/Layout Engineer, Memory CAD, Guadalajara

Micron Technology, Inc • Tlaquepaque

Presencial
MXN 1.387.000 - 1.735.000
Medical, dental, and vision plans
Income protection program
Paid family leave
+1
DRAM Design Layout Engineer – Design Tech Lead
DRAM Design Layout Engineer – Design Tech Lead

Micron • Jalisco

Presencial
MXN 450.000 - 750.000
Pathfinding Senior Design Layout Engineer
Pathfinding Senior Design Layout Engineer

Micron Technology • Tlaquepaque

Presencial
MXN 1.040.000 - 1.561.000
Senior Software Engineer - Data Center Tools & Validation
Senior Software Engineer - Data Center Tools & Validation

Intel • Región Centro

Presencial
MXN 900.000 - 1.500.000
SoC/IP Design Verification Engineer
SoC/IP Design Verification Engineer

Intel • Región Centro

Presencial
MXN 700.000 - 1.100.000