Physical Design Engineer

Intel; Región Centro; Híbrido; MXN 600.000 - 900.000; Jornada completa

Descripción de la vacante

Intel in Guadalajara, Mexico, seeks a Physical Design Engineer to drive RTL-to-GDS implementation for custom IP and SoC designs. You will execute end-to-end physical design flows, including synthesis, floor planning, placement, routing, and timing closure, while optimizing power, performance, and area.

Collaboration across teams and a strong emphasis on design methodology will be key. Ideal candidates bring 3+ years (BS) or 2+ years (MS) in Electrical/Computer Engineering with proficiency in

Formación

• Bachelor’s or BS in Electrical/Computer Engineering with 3+ years of experience.
• Master’s in Electrical/Computer Engineering with 2+ years of experience.
• PhD in Electrical/Computer Engineering with no prior experience.
• RTL-to-GDS implementation and timing closure experience.
• Proficiency in EDA tools for physical design.

Responsabilidades

• Perform physical design implementation of IP and SoC designs from RTL to GDS.
• Execute synthesis, floor planning, place and route, clock tree synthesis, STA, and power distribution.
• Conduct verification and sign-off activities such as formal equivalence verification, STA, power integrity analysis, and layout verification.
• Analyze results to identify and resolve violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry-standard EDA tools.
• Develop and refine physical design methodologies and flow automation to improve team efficiency.
• Collaborate across teams to address design challenges and deliver robust solutions.

Conocimientos

RTL-to-GDS

Cadence

Mentor Graphics

Static Timing Analysis

Low-Power Design

English Proficiency

Educación

Bachelor’s or BS in Electrical/Computer Engineering

Master’s in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Herramientas

Cadence

Mentor Graphics

Descripción del empleo

Job Details

Job Description: As a Physical Design Engineer, you will play a pivotal role in shaping the next generation of custom IP and SoC designs at Intel. Your work will directly influence the cutting‑edge technology that powers our products, driving advancements in performance, efficiency, and innovation. In this role, you will have the opportunity to engage in all aspects of physical design, from RTL to GDS, crafting a design database that is ready for manufacturing. Your expertise in optimizing designs for power, frequency, and area will contribute significantly to Intel’s mission to deliver world‑class technological solutions. This is an exciting opportunity to be at the forefront of physical design engineering, working alongside industry experts to push the boundaries of what is possible in semiconductor technology.

Responsibilities

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
• Execute comprehensive physical design flows, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
• Conduct verification and sign‑off activities such as formal equivalence verification, static timing analysis, power integrity analysis, and layout verification.
• Analyze results to identify and resolve violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry‑standard EDA tools.
• Develop and refine physical design methodologies and flow automation to improve team efficiency and accuracy.
• Collaborate across teams to address design challenges and deliver robust solutions.

Ideal Candidate Behavioral Traits

• Demonstrated experience in solving complex design challenges through innovative and efficient solutions.
• Strong communication skills, willing to work effectively in cross‑functional teams.
• Enthusiasm for contributing to Intel’s mission to deliver leading‑edge technology and innovation.

Qualifications

Minimum qualifications, you must possess the below minimum qualifications to be initially considered for this position:

• Bachelor’s or BS degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of experience.
• OR Master’s degree in Electrical Engineering, Computer Engineering, or a related field with 2+ years of experience.
• OR PhD in Electrical Engineering, Computer Engineering, or a related field with no prior experience.

The experience listed above should be a combination of the following:

• RTL‑to‑GDS implementation, including synthesis, place and route, and timing closure.
• Proficiency in industry‑standard EDA tools such as Cadence or Mentor Graphics for physical design tasks.
• In static timing analysis, floor planning, and power integrity analysis.
• Low‑power design techniques and methodologies.
• Advanced English level.

• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications

• Experience in driving continuous improvement in design methodologies and automation.
• Execution and attention to detail in design implementation.
• Driving continuous improvement in design methodologies and automation.

Job Type

Experienced Hire

Shift

Shift 1 (Mexico)

Primary Location

Mexico, Guadalajara

Business Group

The Central Engineering Group (CEG) is Intel’s data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel’s product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

Additional Information

Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.