Hybrid Physical Design Engineer — RTL to GDS, Power/Area

Intel; Región Centro; Híbrido; MXN 600.000 - 900.000; Jornada completa

Descripción de la vacante

Intel in Guadalajara, Mexico, seeks a Physical Design Engineer to drive RTL-to-GDS implementation for custom IP and SoC designs. You will execute end-to-end physical design flows, including synthesis, floor planning, placement, routing, and timing closure, while optimizing power, performance, and area.

Collaboration across teams and a strong emphasis on design methodology will be key. Ideal candidates bring 3+ years (BS) or 2+ years (MS) in Electrical/Computer Engineering with proficiency in

Formación

• Bachelor’s or BS in Electrical/Computer Engineering with 3+ years of experience.
• Master’s in Electrical/Computer Engineering with 2+ years of experience.
• PhD in Electrical/Computer Engineering with no prior experience.
• RTL-to-GDS implementation and timing closure experience.
• Proficiency in EDA tools for physical design.

Responsabilidades

• Perform physical design implementation of IP and SoC designs from RTL to GDS.
• Execute synthesis, floor planning, place and route, clock tree synthesis, STA, and power distribution.
• Conduct verification and sign-off activities such as formal equivalence verification, STA, power integrity analysis, and layout verification.
• Analyze results to identify and resolve violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry-standard EDA tools.
• Develop and refine physical design methodologies and flow automation to improve team efficiency.
• Collaborate across teams to address design challenges and deliver robust solutions.

Conocimientos

RTL-to-GDS

Cadence

Mentor Graphics

Static Timing Analysis

Low-Power Design

English Proficiency

Educación

Bachelor’s or BS in Electrical/Computer Engineering

Master’s in Electrical/Computer Engineering

PhD in Electrical/Computer Engineering

Herramientas

Cadence

Mentor Graphics

Descripción del empleo

Intel in Guadalajara, Mexico, seeks a Physical Design Engineer to drive RTL-to-GDS implementation for custom IP and SoC designs. You will execute end-to-end physical design flows, including synthesis, floor planning, placement, routing, and timing closure, while optimizing power, performance, and area.

Collaboration across teams and a strong emphasis on design methodology will be key. Ideal candidates bring 3+ years (BS) or 2+ years (MS) in Electrical/Computer Engineering with proficiency in