Pathfinding Senior Design Layout Engineer

Micron Technology; Tlaquepaque; Presencial; MXN 1.040.402 - 1.560.603; Jornada completa

Descripción de la vacante

Micron Technology is seeking a Pathfinding Senior Design Layout Engineer to join its DDR Team in Guadalajara, Mexico. The role involves designing critical analog layouts and ensuring high-quality delivery across projects.

The ideal candidate will possess a strong background in analog layouts, expertise with Cadence tools, and the ability to mentor junior engineers. Micron values collaboration across global teams to drive technology forward in the memory and storage industry.

Formación

• Demonstrated ability in analog/custom layout design in advanced CMOS processes.
• Strong understanding of analog layout fundamentals including matching, electromigration, latch-up.
• Ability to assess circuit-layout interactions including speed and power.

Responsabilidades

• Design and develop critical analog, mixed-signal blocks.
• Perform layout verification activities including LVS and DRC checks.
• Ensure timely delivery of block-level layouts that meet quality expectations.
• Mentor team members during sub-block layout execution.

Conocimientos

Analog/layout design

Expertise with Cadence VLE/VXL

Experience with Mentor Graphics Calibre DRC/LVS

Problem-solving skills in physical verification

Educación

Bachelor’s or Master’s in Electronics, VLSI Engineering

Herramientas

Cadence VLE/VXL

Mentor Graphics Calibre DRC/LVS

Descripción del empleo

Overview

Req ID: JR93766
Pathfinding Senior Design Layout Engineer

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are seeking a Layout Design Engineer to join Micron’s DDR Team in Guadalajara, Mexico. In this role, you will collaborate with global teams in a multi‑project environment to deliver high‑quality layout design solutions across analog, mixed‑signal, and custom digital domains.

Responsibilities

• Design and develop critical analog, mixed‑signal, custom digital blocks, and support full‑chip level integration.
• Perform layout verification activities including LVS, DRC, antenna checks, quality reviews, and documentation.
• Ensure on‑time delivery of block‑level layouts that meet quality expectations.
• Lead planning, area/time estimation, scheduling, delegation, and execution across multiple concurrent projects.
• Mentor and guide developing team members during sub‑block layout execution and review their work.
• Communicate effectively with global engineering teams to ensure layout project success.

Minimum Qualifications

• Demonstrated ability in analog/custom layout design in advanced CMOS processes across various technology nodes (Planar, FinFET).
• Bachelor’s, Master’s, or equivalent experience in Electronics, VLSI Engineering, or a related field.
• Expertise with Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS.
• Hands‑on experience creating layout for critical blocks such as temperature sensors, PLL, ADC, DAC, LDO, bandgap, reference generators, charge pumps, current mirrors, comparators, differential amplifiers, etc.
• Strong understanding of analog layout fundamentals: matching, electromigration, latch‑up, coupling, crosstalk, IR‑drop, and parasitic effects.
• Ability to assess circuit‑layout interactions including speed, capacitance, power, and area.
• Proven ability to interpret design constraints and implement high‑quality layouts.

Preferred Qualifications

• Experience supporting multiple tape‑outs.
• Experience leading multiple layout projects and ensuring quality gates across development stages.
• Strong problem‑solving skills in physical verification of custom layouts.

Other Information

Relocation Level: TBD

Micron is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.