Physical Design Engineer

Intel Corporation; Región Centro; Presencial; MXN 400.000 - 700.000; Jornada completa

Descripción de la vacante

Intel Corporation in Guadalajara, Mexico is seeking a hands-on Physical Design Engineer (EM/IR Closure) to own block-level reliability closure and drive EM/IR signoff within SAM frameworks, collaborating with Physical Design, STA and Methodology teams.

The role requires strong execution, knowledge of Python/Tcl/Perl scripting for design flows, experience with Calibre DRC and Synopsys/Cadence tools, and on-site work authorization in Mexico.

Formación

• Bachelor's or BS degree in Electronics/Computer Engineering or related field with 3+ years experience.
• OR Master's in Electronics/Computer Engineering or related field with 2+ years experience.
• OR PhD in Electronics/Computer Engineering or related field with no experience.
• Proficiency in scripting languages for design flow automation (Python/Tcl/Perl).
• Experience with static timing analysis, layout verification tools (Calibre DRC), and physical clock design.
• Experience in physical design for IP/SoC using Synopsys or Cadence tools.
• Intermediate to advanced English; Mexican work authorization (no visa sponsorship).

Responsabilidades

• Execute physical design implementation from RTL to GDS, including synthesis, P&R, STA, and floor planning.
• Perform verification and signoff: formal verification, reliability checks, power integrity, layout checks, EDA timing analysis.
• Identify violations and recommend architecture improvements.
• Optimize designs to improve power, frequency, and area using standard EDA tools.
• Develop physical design methodologies, automation flows, and processes.
• Collaborate with cross-functional teams to meet Intel's quality and performance standards.

Conocimientos

Python

Tcl

Perl

English (intermediate)

Educación

Bachelor's or BS in Electronics Engineering, Computer Engineering, or related field

Master's in Electronics Engineering, Computer Engineering, or related specialized field

PhD in Electronics Engineering, Computer Engineering, or related specialized field

Herramientas

Synopsys tools

Cadence tools

Calibre DRC

PrimeTime PX

PrimeRail

Redhawk

Descripción del empleo

The Physical Design Engineer (EM/IR Closure Engineer) is a hands‑on individual contributor responsible for block‑level and subsystem‑level EM/IR analysis and closure. The role requires strong execution rigor, ownership of reliability closure for assigned blocks, and close collaboration with Physical Design, STA, and Methodology teams while operating within established SAM signoff frameworks.

Responsibilities

• Execute physical design implementation from RTL to GDS, including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, and power/clock distribution.
• Conduct verification and signoff, including formal equivalence verification, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and timing analysis.
• Identify and resolve violations, making recommendations for current and future product architectures.
• Optimize designs to enhance metrics such as power, frequency, and area using industry‑standard EDA tools.
• Develop and improve physical design methodologies, automation flows, and processes.
• Possess expertise in structural and physical design, including timing closure, physical clock design, and multiple power domain analysis.
• Define and apply constraints for hierarchical design integration and floor planning concepts.
• Collaborate with cross-functional teams to ensure designs meet Intel's quality and performance standards.

Qualifications

Minimum Qualifications are required to be initially considered for this position.

• Bachelor's or BS degree in Electronics Engineering, Computer Engineering, or related specialized field with 3+ years of experience.
• OR Master's degree in Electronics Engineering, Computer Engineering, or related specialized field with 2+ years of experience.
• OR PhD in Electronics Engineering, Computer Engineering, or related specialized field with no experience required.

Experience listed above should be a combination of the following:

• Proficiency in scripting languages (e.g., Python, Tcl, Perl) for design flow automation.
• Expertise in static timing analysis, layout verification tools such as Calibre DRC, and physical clock design.
• Physical design implementation for custom IP and SoC designs using industry‑standard tools such as Synopsys or Cadence.
• Intermediate to advanced English level.
• Must have unrestricted, permanent right to work in Mexico (this role is not eligible for visa or immigration sponsorship).

Preferred Qualifications

• Relevant Physical Design or Signoff experience.
• Working knowledge of Synopsys/Ansys signoff tools such as PrimeTime PX, PrimeRail, Redhawk etc.
• Understanding power delivery networks, reliability fundamentals, and signoff criteria.
• Experience working with Physical Design ECO cycles and closure loops.
• Scripting experience in TCL and/or Python.
• Hands‑on experience with EM/IR analysis and closure for advanced nodes such as 3nm or below.

Requirements listed would be obtained through a combination of relevant industry job experience, internship experience, and/or schoolwork/classes/research.

Job Type: Experienced Hire

Shift: Shift 1 (Mexico)

Primary Location: Mexico, Guadalajara

Additional Locations:

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Work Model for this Role: This role will require an on‑site presence.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.