DRAM IP Layout Intern — Automation & Verification

micron

Xalisco

Presencial

MXN 134.000 - 201.000

Jornada completa

Hace 5 días

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Descripción de la vacante

Micron Technology is seeking a Layout Design Engineering Intern to contribute to the development and verification of IP layout cells used in memory products. You will learn floorplanning, placement, routing, and physical verification alongside seasoned layout engineers.

You will also help develop automation solutions to boost productivity and design quality using scripting and AI-assisted development.

Formación

Pursuing a Bachelor's degree in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, or related field.
Expected graduation date December 2027.
Experience with at least one scripting language such as Python, Perl, or similar.
Strong time management and organizational skills with the ability to work efficiently on multiple tasks.
Effective verbal and written communication skills.

Responsabilidades

Develop the layout of selected analog and digital IP layout cells under guidance.
Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification and document findings.
Create and deliver technical reports summarizing design work and verification results.
Design and implement a SKILL-based automation solution to improve layout design or verification processes.
Support engineering activities through AI-assisted development methodologies and productivity tools.