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QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA seeks an experienced DDR Validation Engineer to lead end-to-end validation of LPDDR5X/LPDDR6 memory subsystems across AI Accelerator and flagship platforms. You will drive bring-up, training validation, and system-level debugging from pre- to post-silicon stages.
The role demands strong C/C++ development skills, post-silicon debugging proficiency, and collaboration with architecture, design, firmware, and DRAM vendors to ensure
QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA
Engineering Group, Engineering Group > ASICS Engineering
Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases .
This team focuses on content quality and system-level validation enablement , offering deep exposure to Qualcomm SoCs through bare-metal validation content , scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content , ensuring high-quality silicon validation across a wide range of SoC domains.
We are seeking an experienced DDR Validation Engineer for end-to-end validation of next-generation LPDDR5X and LPDDR6 memory subsystems on AI Accelerator and Flagship mobile platforms. This role will lead memory bring-up, performance validation, system stress, debug, and production readiness from pre-silicon through post-silicon phases.
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