Soc Physical Design Engineer

Nokia; Macerata; Hybrid; EUR 60,000 - 90,000; Full time

Benefits offered by this job

Flexible work arrangement

Parental leave

Life insurance

Well-being programs

NERG participation

Career development

Job summary

Nokia is seeking a SoC Physical Design Engineer to implement physical design for Optical Network ASICs across cutting-edge nodes in a hybrid working environment. You will perform floorplanning, placement, routing, and timing closure, collaborating with RTL designers and hardware teams to optimize power, performance, and area.

The role requires 3+ years of ASIC PD experience on 3/5/7nm, strong RTL to GDSII knowledge, and proficiency with Fusion Compiler, Innovus, Primetime, Calibre, and Redhawk.

Qualifications

• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes.
• Solid knowledge of RTL to GDSII and underlying IC design concepts.
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk.
• Scripting experience in TCL, Python or Perl.
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics.
• Strong collaboration with cross-functional teams.
• Team collaboration, analytical mindset, problem solving.

Responsibilities

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Skills

ASIC physical design

Floorplanning

Place & route

Timing closure

RTL to GDSII

Scripting (TCL/Python/Perl)

Cross-functional collaboration

Power/clock distribution

Education

Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics

Tools

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Job description

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and design methodologies. The opportunity centers on delivering best-in-class silicon while learning the latest nodes and tools. You will contribute to a mission-driven environment that values automation and rigorous verification.

• Flexible and hybrid working schemes
• Parental leave (90 days) with return option
• Life insurance for employees
• Well-being programs for mental and physical health
• Participation in Nokia Employee Resource Groups (NERGs)
• Career development and coaching/mentoring
• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs
• Evaluate IP vendors, process nodes, and provide actionable recommendations
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing
• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes
• Solid knowledge of RTL to GDSII and underlying IC design concepts
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk
• Scripting experience in TCL, Python or Perl
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics
• Strong collaboration with cross-functional teams
• team collaboration
• analytical mindset
• problem solving
• Floorplanning and placement/routing

SoC Physical Design Engineer macerata, marche, it