SoC Physical Design Engineer — Hybrid, Cutting-Edge ASIC

Nokia; Macerata; Híbrido; EUR 60.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible work arrangement

Parental leave

Life insurance

Well-being programs

NERG participation

Career development

Descripción de la vacante

Nokia is seeking a SoC Physical Design Engineer to implement physical design for Optical Network ASICs across cutting-edge nodes in a hybrid working environment. You will perform floorplanning, placement, routing, and timing closure, collaborating with RTL designers and hardware teams to optimize power, performance, and area.

The role requires 3+ years of ASIC PD experience on 3/5/7nm, strong RTL to GDSII knowledge, and proficiency with Fusion Compiler, Innovus, Primetime, Calibre, and Redhawk.

Formación

• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes.
• Solid knowledge of RTL to GDSII and underlying IC design concepts.
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk.
• Scripting experience in TCL, Python or Perl.
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics.
• Strong collaboration with cross-functional teams.
• Team collaboration, analytical mindset, problem solving.

Responsabilidades

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Conocimientos

ASIC physical design

Floorplanning

Place & route

Timing closure

RTL to GDSII

Scripting (TCL/Python/Perl)

Cross-functional collaboration

Power/clock distribution

Educación

Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics

Herramientas

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descripción del empleo

Nokia is seeking a SoC Physical Design Engineer to implement physical design for Optical Network ASICs across cutting-edge nodes in a hybrid working environment. You will perform floorplanning, placement, routing, and timing closure, collaborating with RTL designers and hardware teams to optimize power, performance, and area.

The role requires 3+ years of ASIC PD experience on 3/5/7nm, strong RTL to GDSII knowledge, and proficiency with Fusion Compiler, Innovus, Primetime, Calibre, and Redhawk.