Soc Physical Design Engineer

Nokia Global; Italia; In loco; EUR 50.000 - 80.000; Tempo pieno

Descrizione del lavoro

Nokia Global sta cercando un SoC Physical Design Engineer per l’implementazione fisica di ASIC per reti ottiche. Progetterà flow, eseguirà floorplanning, place & route, clock/power distribution e timing closure, collaborando con team di logica e hardware.

Relazione al team di ingegneria pubblica, con focalizzazione su ottimizzazione di potenza, prestazioni e area in nodi avanzati. Laurea in discipline correlate richiesta, ruolo a tempo pieno in Italia.

Competenze

• 3+ anni di esperienza nei flussi di progettazione fisica ASIC in nodi 3/5 e 7nm
• Conoscenza del ciclo completo di progettazione RTL a GDSII e concetti di design IC
• Esperienza con strumenti EDA di Place & Route e strumenti di timing e PV/IR

Mansioni

• Eseguire fasi di implementazione fisica tra cui floorplanning, place & route, distribuzione power/clock, verifica fisica e timing closure a blocchi e chip intero
• Collaborare con progettisti logici e hardware per studi di fattibilità e trade-off
• Valutare fornitori IP e processi e fornire raccomandazioni
• Sviluppare metodologie di progettazione fisica e script di automazione per le fasi di implementazione dalla sintesi al GDSII
• Eseguire static timing analysis, creare constraint temporali e validazione, analisi del path critico e timing sign-off
• Eseguire verifiche fisiche e analisi IR/EM su blocchi e su top-level

Conoscenze

ASIC physical design

Scripting TCL/Python/Perl

RTL to GDSII understanding

Formazione

Laurea in Elettronica/VLSI/Microelettronica

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

SoC Physical Design Engineer

Azienda : Nokia Global Tipo Lavoro : Full Time Italy

Descrizione Lavoro - SoC Physical Design Engineer

You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics.

NION2026

Responsibilities

• Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip
• Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure
• Perform technical evaluations of IP vendors, process nodes and provide recommendations
• Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
• Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
• Perform Physical verification and IR/EM analysis on blocks as well as top

Qualifications

• 3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
• Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
• Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar, PV tools like Calibre and IR tools like Redhawk
• Scripting experience in TCL, python or Perl
• Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics

Informazioni sull'azienda

Nokia Global

Advancing connectivity to secure a brighter world. Nokia is a global leader in connectivity for the AI era. With expertise across fixed, mobile and transport networks, powered by the innovation of Nokia Bell Labs, we’re advancing connectivity to secure a brighter world. Learn more about life at Noki...