Soc Physical Design Engineer

Nokia; Terni; Ibrido; EUR 65.000 - 100.000; Tempo pieno

Vantaggi offerti da questo lavoro

Flexible and hybrid working schemes

Parental leave (90 days)

Life insurance for employees

Well-being programs for mental and физ

NERGs

Career development and coaching/mentor

Descrizione del lavoro

Nokia in Umbria, Italy seeks a SoC Physical Design Engineer to drive floorplanning, placement, routing and timing closure for 3/5/7nm ASICs. You will optimize power, performance and area within a hardware/RTL team, translating designs into silicon and advancing PD methodologies.

Collaborate with RTL designers, run IV/DT verifications, and develop automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.

Competenze

• 3+ years of ASIC physical design experience.
• Experience on 3/5/7nm nodes.

Mansioni

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Conoscenze

ASIC PD flow

RTL to GDSII

Floorplanning

Timing closure

EDA tools

Scripting TCL

Python

Collaboration

Formazione

Bachelor's degree in Electrical/Electronics

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

In this role, you will implement physical design for Optical Network ASICs across cutting-edge nodes, focusing on power, performance, and area. You will work within a hardware/RTL team to translate designs into silicon and optimize flows for submicron processes. You’ll tackle floorplanning, placement, routing, and timing closure, shaping multi-project IP and design methodologies. The opportunity centers on delivering best-in-class silicon while learning the latest nodes and tools. You will contribute to a mission-driven environment that values automation and rigorous verification.

• Flexible and hybrid working schemes
• Parental leave (90 days) with return option
• Life insurance for employees
• Well-being programs for mental and physical health
• Participation in Nokia Employee Resource Groups (NERGs)
• Career development and coaching/mentoring
• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs
• Evaluate IP vendors, process nodes, and provide actionable recommendations
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing
• 3+ years of experience in ASIC physical design flow and methodologies on 3/5/7nm nodes
• Solid knowledge of RTL to GDSII and underlying IC design concepts
• Experience with EDA tools: Fusion Compiler or Innovus, Primetime or equivalent, Calibre, Redhawk
• Scripting experience in TCL, Python or Perl
• Bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics
• Strong collaboration with cross-functional teams
• team collaboration
• analytical mindset
• problem solving
• Floorplanning and placement/routing

SoC Physical Design Engineer terni, umbria, it