SoC Physical Design Engineer for Next-Gen ASICs

Nokia; Terni; Ibrido; EUR 65.000 - 100.000; Tempo pieno

Vantaggi offerti da questo lavoro

Flexible and hybrid working schemes

Parental leave (90 days)

Life insurance for employees

Well-being programs for mental and физ

NERGs

Career development and coaching/mentor

Descrizione del lavoro

Nokia in Umbria, Italy seeks a SoC Physical Design Engineer to drive floorplanning, placement, routing and timing closure for 3/5/7nm ASICs. You will optimize power, performance and area within a hardware/RTL team, translating designs into silicon and advancing PD methodologies.

Collaborate with RTL designers, run IV/DT verifications, and develop automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.

Competenze

• 3+ years of ASIC physical design experience.
• Experience on 3/5/7nm nodes.

Mansioni

• Perform floorplanning, place & route, and power/clock distribution for blocks and full chips.
• Execute physical verification, IR/EM analysis, and timing closure at block and chip level.
• Collaborate with logic designers and hardware teams on feasibility studies and design trade-offs.
• Evaluate IP vendors, process nodes, and provide actionable recommendations.
• Develop PD methodologies and automation scripts for steps from Synthesis to GDSII.
• Conduct static timing analysis, create timing constraints, validate critical paths, and sign off timing.

Conoscenze

ASIC PD flow

RTL to GDSII

Floorplanning

Timing closure

EDA tools

Scripting TCL

Python

Collaboration

Formazione

Bachelor's degree in Electrical/Electronics

Strumenti

Fusion Compiler

Innovus

Primetime

Calibre

Redhawk

Descrizione del lavoro

Nokia in Umbria, Italy seeks a SoC Physical Design Engineer to drive floorplanning, placement, routing and timing closure for 3/5/7nm ASICs. You will optimize power, performance and area within a hardware/RTL team, translating designs into silicon and advancing PD methodologies.

Collaborate with RTL designers, run IV/DT verifications, and develop automation scripts using TCL/Python to streamline Synthesis through GDSII for multi-project IPs.