Senior HS Digital Design Engineer – SoC RTL Lead

ams Italy S.r.l.; Vigevano; In loco; EUR 90.000 - 130.000; Tempo pieno

Descrizione del lavoro

ams Italy S.r.l. is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products.

You will define architectures, lead RTL design and integration, and drive design reviews to ensure quality. The ideal candidate has MSc or PhD in Electrical Engineering with 10+ years of digital IC design experience, strong Verilog/SystemVerilog skills, and hands-on experience with high-speed interfaces and timing

Competenze

• MSc or PhD in Electrical Engineering.
• 10+ years of digital IC design experience.
• RTL design using Verilog or SystemVerilog.
• Experience with high-speed interfaces (UCIe, PCIe or similar) preferred.
• Knowledge of clock-domain crossing and interface protocols.

Mansioni

• Define digital subsystem architectures.
• Lead RTL development and integration.
• Drive design reviews and quality standards.
• Support verification and implementation teams.
• Mentor design engineers.

Conoscenze

RTL design (Verilog/SystemVerilog)

High-speed digital IC design

Interface protocols and CDC

Synthesis and timing analysis

10+ years digital IC design experience

Formazione

MSc or PhD in Electrical Engineering

Descrizione del lavoro

ams Italy S.r.l. is seeking a technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products.

You will define architectures, lead RTL design and integration, and drive design reviews to ensure quality. The ideal candidate has MSc or PhD in Electrical Engineering with 10+ years of digital IC design experience, strong Verilog/SystemVerilog skills, and hands-on experience with high-speed interfaces and timing