Senior Digital IC Design Engineer (RTL/Verilog)

NXP Semiconductors; Catania; Sur place; EUR 51 000 - 70 000; Plein temps

Avantages offerts par ce poste

Annual incentive opportunities

Equity participation

Comprehensive benefits package

Learning and development programs

Résumé du poste

NXP Semiconductors in Italy (Catania) is seeking a Master’s-level IC design engineer to develop digital sub-circuits for SOCs using Verilog/SystemVerilog, RTL techniques and advanced verification.

You will collaborate with analog, mixed-signal and software teams to optimize interfaces, perform design verification, participate in post-silicon validation and contribute to high-quality, testable ICs.

Qualifications

• Master's degree in Electrical Engineering, Electronics Engineering, or related field.
• Expertise in Verilog/SystemVerilog for RTL design and verification.
• Experience with scripting languages (Python, Perl, Tcl) for automation and design flow.

Responsabilités

• Develop digital sub-circuits for SOCs based on pre-defined specifications.
• RTL coding, synthesis, STA and formal verification.
• Contribute to DFT implementation and verification.
• Collaborate with analog, mixed-signal, and software teams to define interfaces.
• Perform design verification using simulation, formal verification, and emulation.
• Generate design documentation and participate in post-silicon validation.

Connaissances

Verilog/SystemVerilog

RTL design & verification

Scripting: Python/Perl/Tcl

EDA tools familiarity

Team collaboration

Formation

Master's degree in Electrical Engineering or Electronics Engineering

Outils

EDA tools

Description du poste

NXP Semiconductors in Italy (Catania) is seeking a Master’s-level IC design engineer to develop digital sub-circuits for SOCs using Verilog/SystemVerilog, RTL techniques and advanced verification.

You will collaborate with analog, mixed-signal and software teams to optimize interfaces, perform design verification, participate in post-silicon validation and contribute to high-quality, testable ICs.