Principal HS Digital Design Engineer (d/m/f)

Ams Osram; Italia; In loco; EUR 90.000 - 150.000; Tempo pieno

Descrizione del lavoro

ams OSRAM’s LSP unit seeks a Technical Leader to own architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products. You define digital subsystem architectures and lead RTL development and integration.

You will drive design reviews, support verification and implementation teams, and mentor design engineers, leveraging an MSc/PhD in Electrical Engineering and 10+ years of digital IC design experience.

Competenze

• MSc or PhD in Electrical Engineering is required.
• 10+ years of digital IC design experience.
• RTL design using Verilog or SystemVerilog.
• Experience with high-speed interfaces such as UCIe or PCIe is an advantage.
• Knowledge of interface protocols and clock-domain crossing.
• Synthesis and timing analysis expertise.
• Advanced CMOS node experience (FinFET/FD-SOI) is required.

Mansioni

• Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products.
• Define digital subsystem architectures.
• Lead RTL development and integration.
• Drive design reviews and quality standards.
• Support verification and implementation teams.
• Mentor design engineers.

Conoscenze

RTL design

High-speed digital IC design

Interface protocols

Clock-domain crossing

Synthesis and timing analysis

FinFET/FD-SOI experience

Formazione

MSc or PhD in Electrical Engineering

Descrizione del lavoro

We are LSP – Light Sensors & Photonics, one of three business units within ams OSRAM, advancing the digitalization of light. At LSP, we go beyond traditional sensing—combining light, silicon, and system expertise to enable digital photonics solutions. Our focus is clear: powering next-generation applications in data centers, AR/VR, mobile and automotive, where light becomes a critical interface for data, perception, and interaction. This evolution marks a shift from components to integrated photonics systems —driving performance, scalability, and innovation in high-growth segments.

• Technical leader responsible for architecture and RTL development of high-speed digital subsystems for communication ICs and mixed-signal SoC products
• Define digital subsystem architectures
• Lead RTL development and integration
• Drive design reviews and quality standards
• Support verification and implementation teams
• Mentor design engineers

• MSc or PhD in Electrical Engineering
• 10+ years digital IC design experience
• RTL design (Verilog/SystemVerilog)
• High-speed digital IC design experience for communication or mixed-signal SoC products is required; knowledge of high-speed interfaces such as UCIe, PCIe or similar protocols is an advantage
• Interface protocols and clock-domain crossing
• Synthesis and timing analysis
• Advanced CMOS node experience, including FinFET and/or FD-SOI, is required