Synthesis Engineer 0423

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is seeking a Synthesis Engineer with 3-6 years of experience to join a reputed client project. You will work on STA, timing constraints, and VLSI design flow to deliver robust timing solutions.

The role emphasizes developing and verifying block-level and SoC timing constraints, and integrating IP timing constraints into system constraints while debugging timing issues. Contract tenure is 12 months.

Qualifications

• Proficient in STA concepts and timing constraints (SDC).
• Experience in developing and integrating SoC/block-level constraints.
• Solid understanding of VLSI design flow and methodologies.
• Familiarity with Verilog, Liberty (.lib), LEF and GDS formats.
• Basic knowledge of DRC/LVS physical verification.
• Scripting skills in Tcl, Perl, Unix shell or Python.

Responsibilities

• Develop and verify block-level and SoC timing constraints.
• Integrate IP timing constraints into SoC constraints and debug timing issues.
• Collaborate with RTL/physical teams to ensure timing closure.

Skills

STA concepts & SDC

SoC/block-level constraints

VLSI design flow

Verilog, Liberty, LEF, GDS

DRC/LVS knowledge

Tcl/Perl/Python scripting

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Synthesis Engineer
Experience: 3-6 Years

Location: Hyderabad

Contract Tenure : 12 months

Job Description:
We are looking for an engineer with a strong understanding of Static Timing Analysis (STA), timing constraints, and VLSI design flow. Responsibilities include developing and verifying block-level and SoC-level timing constraints, integrating IP timing constraints into SoC constraints, and debugging timing constraint issues.

Required Skills:

• STA concepts and timing constraints (SDC).
• SoC and block-level constraint development and integration.
• VLSI design flow knowledge.
• Familiarity with Verilog, Liberty (.lib), LEF, and GDS.
• Basic knowledge of DRC/LVS physical verification.
• Scripting skills in Tcl, Perl, Unix Shell, or Python.