Lead STA & Synthesis Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

LeadSOC Technologies Pvt Ltd in Bengaluru seeks a Lead STA & Synthesis Engineer with hands-on expertise in Static Timing Analysis, RTL Synthesis, timing closure, and implementation flows for complex SoC designs.

You will own RTL-to-gate synthesis and timing analysis, drive constraints and closure across MCMM/MMC scenarios, and develop SDC constraints, clocks, and timing paths. Strong Synopsys tool experience and scripting skills are essential for flow automation.

Qualifications

• 8–12 years of STA, synthesis, or front-end implementation.
• Strong experience with Synopsys tools (CD/ Fusion).
• Hands-on with PrimeTime and timing analysis.
• Experience with RTL synthesis, timing optimization and ECO flows.
• Background in ASIC/SoC implementation and signoff.

Responsibilities

• Own RTL-to-gate synthesis and timing analysis for complex SoC/IP designs.
• Drive STA, timing constraints, and timing closure across MCMM/MMC scenarios.
• Develop, validate, and debug SDC constraints, clocks, exceptions, and timing paths.
• Perform setup/hold analysis, critical path analysis, and timing optimization.
• Work with RTL, Physical Design, DFT, and implementation teams to resolve timing issues.
• Analyze and optimize area, power, and performance during synthesis.
• Drive ECOs and timing fixes through implementation and signoff.
• Debug synthesis/STA issues including unconstrained paths, false paths, clock interactions, and constraint violations.
• Develop scripts and automation using Tcl/Python/Perl to improve flow efficiency.

Skills

STA

RTL synthesis

Timing analysis

ECO flows

Scripting Tcl

Python scripting

Perl scripting

Timing closure

Tools

Design Compiler

Fusion Compiler

PrimeTime

Job description

We are looking for a Lead STA & Synthesis Engineer with strong hands-on expertise in Static Timing Analysis, RTL Synthesis, timing closure, and implementation flows for complex SoC designs.

Key Responsibilities

• Own RTL-to-gate synthesis and timing analysis for complex SoC/IP designs.
• Drive STA, timing constraints, and timing closure across MCMM/MMC scenarios.
• Develop, validate, and debug SDC constraints, clocks, exceptions, and timing paths.
• Perform setup/hold analysis, critical path analysis, and timing optimization.
• Work closely with RTL, Physical Design, DFT, and implementation teams to resolve timing issues.
• Analyze and optimize area, power, and performance (PPA) during synthesis.
• Drive ECOs and timing fixes through implementation and signoff.
• Debug synthesis/STA issues including unconstrained paths, false paths, clock interactions, and constraint violations.
• Develop scripts and automation using Tcl/Python/Perl to improve flow efficiency.

Core Technical Requirements

• 8-12 years of experience in STA, synthesis, or front-end implementation.
• Strong expertise in Synopsys Design Compiler / Fusion Compiler or equivalent synthesis tools.
• Strong hands-on experience with Synopsys PrimeTime or equivalent STA tools.
• Deep understanding of SDC, MCMM/MMC, setup/hold, clocking, OCV/AOCV/POCV, and timing exceptions.
• Experience with RTL synthesis, timing optimization, and ECO flows.
• Strong understanding of ASIC/SoC implementation and signoff methodologies.
• Proficiency in Tcl/Python/Perl scripting.
• Experience with advanced technology nodes and complex SoC designs is preferred.