STA/Synthesis Engineer - Mumbai

N Human Resources & Management Systems; Mumbai; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

N Human Resources & Management Systems in Mumbai is seeking an STA/Synthesis Engineer to own synthesis and timing signoff from RTL through tapeout. You will drive timing closure and collaborate with RTL and Physical Design teams to ensure successful SoC timing.

We expect 4+ years in STA and Synthesis, strong TCL scripting, and deep knowledge of timing signoff flows. Join a hands-on VLSI delivery team and mentor 4–5 engineers on STA practices.

Qualifications

• 4+ years of hands-on STA and Synthesis experience.
• Strong TCL scripting and Unix environment skills.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Own synthesis and STA across design blocks and drive timing signoff from RTL to tapeout.
• Develop and maintain SDC/UPF constraints including DFT-aware constraints.
• Perform pre- and post-layout timing closure across corners and modes.
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner with RTL design and Physical Design teams on SoC timing closure
• Drive manual ECO generation to resolve timing and DRC violations

Skills

STA & Synthesis

Unix environment

Timing signoff flows

Constraint development

Tools

TCL scripting

Job description

N Human Resources & Management Systems | Full time

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• - Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• - SDC and UPF constraint development, including DFT-aware constraints
• - Pre- and post-layout timing closure across corners and modes
• - Manual ECO generation to resolve timing and DRC violations
• - Timing closure at block, subsystem and full-chip level
• - Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• - Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• - 4+ years of hands-on experience in STA and Synthesis
• - Strong TCL scripting and Unix environment skills
• - Comprehensive knowledge of timing signoff flows and constraint development