STA/Synthesis Engineer - Coimbatore

N Human Resources & Management Systems; Coimbatore District; On-site; INR 900,000 - 1,350,000; Full time

Job summary

N Human Resources & Management Systems in Coimbatore is seeking a STA/Synthesis Engineer to own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Responsibilities include logic-aware synthesis, constraint development for SDC/UPF, pre- and post-layout timing closure, and mentoring a team of 4–5 engineers while collaborating with RTL and Physical Design teams.

Qualifications

• 4+ years of hands-on experience in STA and Synthesis.
• Strong TCL scripting and Unix environment skills.
• Comprehensive knowledge of timing signoff flows and constraint development.

Responsibilities

• Logic-aware synthesis, LEC, and VCLP signoff.
• SDC and UPF constraint development, including DFT-aware constraints.
• Pre- and post-layout timing closure across corners and modes.
• Manual ECO generation to resolve timing and DRC violations.
• Timing closure at block, subsystem and full-chip level.
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices.
• Partner closely with RTL design and Physical Design teams on SoC timing closure.

Skills

STA & Synthesis

TCL scripting

Unix environment

Timing signoff

Job description

N Human Resources & Management Systems | Full time

STA/Synthesis Engineer - Coimbatore

Coimbatore, India | Posted on 09/14/2026

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• SDC and UPF constraint development, including DFT-aware constraints
• Pre- and post-layout timing closure across corners and modes
• Manual ECO generation to resolve timing and DRC violations
• Timing closure at block, subsystem and full-chip level
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• 4+ years of hands-on experience in STA and Synthesis
• Strong TCL scripting and Unix environment skills
• Comprehensive knowledge of timing signoff flows and constraint development