STA/Synthesis Engineer - Ahmedabad

N Human Resources & Management Systems; Ahmedabad District; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

N Human Resources & Management Systems in Ahmedabad, India, is hiring a STA/Synthesis Engineer to own synthesis and timing analysis from RTL to tapeout. You will drive timing signoff and collaborate with RTL design and Physical Design teams.

The role requires 4+ years of hands-on STA and Synthesis, strong TCL scripting, and Unix proficiency to develop constraints and meet DRC/Timing goals across corners and modes. You'll lead a small team while delivering reliable timing closures.

Qualifications

• 4+ years hands-on STA and Synthesis experience.
• Strong TCL scripting and Unix skills.
• Deep knowledge of timing signoff flows and constraint development.

Responsibilities

• Logic-aware synthesis, LEC, and VCLP signoff
• SDC and UPF constraint development, including DFT-aware constraints
• Pre- and post-layout timing closure across corners and modes
• Manual ECO generation to resolve timing and DRC violations
• Timing closure at block, subsystem and full-chip level
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• Partner closely with RTL design and Physical Design teams on SoC timing closure

Job description

N Human Resources & Management Systems | Full time

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• - Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• - SDC and UPF constraint development, including DFT-aware constraints
• - Pre- and post-layout timing closure across corners and modes
• - Manual ECO generation to resolve timing and DRC violations
• - Timing closure at block, subsystem and full-chip level
• - Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• - Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• - 4+ years of hands-on experience in STA and Synthesis
• - Strong TCL scripting and Unix environment skills
• - Comprehensive knowledge of timing signoff flows and constraint development