STA Timing Constraints Engineer 0421

Sunrise Biztech Systems; Bengaluru; On-site; INR 1,200,000 - 1,700,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. is hiring for a SoC Timing Constraints Engineer in Bangalore to join our client project. The role focuses on developing and verifying block- and SoC-level timing constraints and ensuring IP timing constraints integrate smoothly into the overall flow.

The ideal candidate has 3–6 years of experience in STA, Verilog-based flows, and scripting skills in Tcl, Perl, Python, or Unix shell. This is a 12-month contract position on site in Bangalore.

Qualifications

• Strong understanding of STA and timing constraints in VLSI design flows.
• Ability to develop and integrate SoC/block-level timing constraints.
• Experience debugging timing constraint issues and constraints integration.

Responsibilities

• Develop and verify block-level and SoC-level timing constraints.
• Integrate IP timing constraints into the SoC constraint framework.
• Debug timing constraint issues across the design flow.

Skills

STA concepts

timing constraints

VLSI design flow

Scripting (Tcl, Perl, Python)

Verilog

Tools

Verilog

Liberty (.lib)

LEF

GDS

Tcl

Perl

Python

Unix Shell

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: SoC Timing Constraints Engineer

Experience: 3-6 Years

Location: Bangalore

Contract Tenure : 12 months

Job Description:

We are looking for an engineer with a strong understanding of Static Timing Analysis (STA), timing constraints, and VLSI design flow. Responsibilities include developing and verifying block-level and SoC-level timing constraints, integrating IP timing constraints into SoC constraints, and debugging timing constraint issues.

Required Skills:

• STA concepts and timing constraints (SDC).
• SoC and block-level constraint development and integration.
• VLSI design flow knowledge.
• Familiarity with Verilog, Liberty (.lib), LEF, and GDS.
• Basic knowledge of DRC/LVS physical verification.
• Scripting skills in Tcl, Perl, Unix Shell, or Python.