RTL Synthesis and STA

Acesoft Labs; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Acesoft Labs is seeking an STA & Synthesis Engineer for our Bangalore/Hyderabad teams. The role focuses on RTL synthesis, timing convergence, and DFT insertions, delivering optimized designs while coordinating with RTL and PD teams to ensure timing closure.

The ideal candidate has 3+ years of hands-on experience with Genus/Tempus/Innovus and strong problem-solving and collaboration skills for a fast-paced hardware team.

Qualifications

• Hands-on RTL synthesis and timing convergence experience.
• Experience with DFT insertions such as MBIST/SCAN is a plus.
• Ability to release blocks RTL to netlist with timing QOR and CLP cleanup.
• Ability to develop synthesis constraints from scratch and support timing closure.

Responsibilities

• Perform RTL synthesis to optimize performance, power and area.
• Implement DFT inserts (MBIST/SCAN) and set up timing constraints for functional and test modes.
• Collaborate with RTL/PD teams to identify RTL changes for timing convergence.
• Release complex blocks from RTL to netlist with timing validation and CLP cleanup.

Skills

RTL synthesis

Timing analysis

DFT constraints

Scripting/constraint development

Team collaboration

Tools

Genus

Tempus

Innovus

Job description

Dear Candidate,

We are hiring for our esteemed client for the role STA & Synthesis Engineer.

Exp - 3+ Years

NP - Immediate to 15 Days

Location - Bangalore, Hyd (WFO)

JD -

Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation.

• Proven hands-on experience on Design compiler/Genus/Fusioncompiler
• Experience timing analysis/debug and driving the timing convergence for complex blocks and release the netlists to PD team
• Ability to own and release the complex blocks from RTL to netlist with timing QOR, CLP cleanup, Check timing, DFT constraint integration.
• Ability to work with RTL design team to identify the must changes in RTL to coverge the timing and work with PD teams to analyze the post route timing and support the final timing closure.
• Hands-on experience constraint development for synthesis from scratch is a plus
• Excellent problem-solving skills.
• Team player with great interpersonal communication skills.
• Experience : 3-7 years
• Tools : Genus/Tempus/Innovus

Based out of Hyderabad/Bangalore location.