SoC Timing Constraints Engineer 0421

Sunrise Biztech Systems; Bengaluru; Vor Ort; INR 1.600.000 - 2.200.000; Vollzeit

Zusammenfassung

Sunrise Biztech Systems Pvt. Ltd. is seeking a SoC Timing Constraints Engineer in Bangalore for a 12-month contract. The role focuses on developing and verifying timing constraints at block and SoC levels, integrating IP timing constraints, and debugging constraint issues.

The candidate should be proficient with STA concepts, SDC timing constraints, and have experience with VLSI design flow, Verilog, and standard physical verification formats.

Qualifikationen

• We are looking for an engineer with strong STA understanding and clear timing constraints knowledge.

Aufgaben

• Develop and verify block-level and SoC-level timing constraints.

Kenntnisse

STA concepts

Timing constraints (SDC)

SoC & block-level constraint dev

VLSI design flow knowledge

Tools

Verilog

Liberty (.lib)

LEF

GDS

Jobbeschreibung

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: SoC Timing Constraints Engineer

Experience: 3-6 Years

Location: Bangalore

Contract Tenure : 12 months

Job Description:

We are looking for an engineer with a strong understanding of Static Timing Analysis (STA), timing constraints, and VLSI design flow. Responsibilities include developing and verifying block-level and SoC-level timing constraints, integrating IP timing constraints into SoC constraints, and debugging timing constraint issues.

Required Skills:

• STA concepts and timing constraints (SDC).
• SoC and block-level constraint development and integration.
• VLSI design flow knowledge.
• Familiarity with Verilog, Liberty (.lib), LEF, and GDS.
• Basic knowledge of DRC/LVS physical verification.
• Scripting skills in Tcl, Perl, Unix Shell, or Python.