STA/Synthesis Engineer - Hyderabad

N Human Resources & Management Systems; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

N Human Resources & Management Systems in Hyderabad, India, is hiring an STA/Synthesis Engineer to own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout. You will lead a small team of 4–5 engineers, mentor them on STA/Synthesis practices, and partner closely with RTL design and Physical Design teams to ensure SoC timing closure.

Experience: 4+ years in STA and synthesis; strong TCL scripting; Unix environment; expertise in timing signoff

Qualifications

• 4+ years hands-on STA and Synthesis experience.
• Proficient TCL scripting.
• Strong Unix environment skills.
• Knowledge of timing signoff flows and constraint development.

Responsibilities

• Logic-aware synthesis, LEC, and VCLP signoff.
• SDC and UPF constraint development, including DFT-aware constraints.
• Pre- and post-layout timing closure across corners and modes.
• Manual ECO generation to resolve timing and DRC violations.
• Timing closure at block, subsystem and full-chip level.
• Lead and mentor a team of 4-5 engineers on STA/Synthesis practices.
• Partner closely with RTL design and Physical Design teams on SoC timing closure.

Skills

TCL scripting

Unix

STA

Synthesis

Timing signoff

Mentoring

Tools

Synthesis tools

Job description

N Human Resources & Management Systems | Full time

We are hiring an STA/Synthesis Engineer to join our VLSI delivery team. You will own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout.

Key Responsibilities:

• - Logic-aware synthesis, logical equivalence checks (LEC), and VCLP signoff
• - SDC and UPF constraint development, including DFT-aware constraints
• - Pre- and post-layout timing closure across corners and modes
• - Manual ECO generation to resolve timing and DRC violations
• - Timing closure at block, subsystem and full-chip level
• - Lead and mentor a team of 4-5 engineers on STA/Synthesis practices
• - Partner closely with RTL design and Physical Design teams on SoC timing closure

Requirements:

• - 4+ years of hands-on experience in STA and Synthesis
• - Strong TCL scripting and Unix environment skills
• - Comprehensive knowledge of timing signoff flows and constraint development