Hardware Design Engineer - 1855

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,200,000 - 1,700,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is seeking an experienced Hardware Design Engineer (5-7 years) to work on STA, timing constraints, and LEC. The role requires interaction with cross-functional teams to ensure timing closure and robust design.

The candidate should have BE/BTech/MTech in Electronics/VLSI or related field and hands-on experience with Verilog and EDA tools. This is a 1-year contract tenure based in Hyderabad.

Qualifications

• Experience in timing constraints, STA and LEC implementations.
• Exposure to industry standard EDA tools and methodologies.
• Strong understanding of digital logic design and timing constraints.

Responsibilities

• Develop constraints for different timing modes (Functional, Scan).
• Perform static timing checks and debug timing issues.
• Debug Formality/Conformal LEC issues and collaborate with cross-functional teams.

Skills

STA engineers

Constraint writing

Static timing analysis

Formality & LEC

Timing CDC crossing

Conformal/Netlist ECO

Communication & cross-functional

Education

B.E/B.Tech/M.Tech in Electronics, VLSI or related field

Tools

EDA tools

Scripting

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Hardware Design Engineer
Experience: 5 - 7 Years

Location: Hyderabad

Contract tenure: 1 year

Top 3 skills:

• STA Engineers, Constraint writing of different timing modes,
• Static timing analysis of different modes
• Formality & LEC
  
• Good to have (secondary) skills:
• Timing CDC crossing understanding
• Conformal or Netlist based ECO implementation
• Strong communication skills and able to interact with different cross functional teams
• Education Background: B.Tech / M.Tech in Electronics, VLSI or related field

Job DescriptionWe are looking for an experienced STA Engineers to join our team in Hyderabad. In this role, you will learn and contribute to implementation activities like timing constraints, STA, logical equivalence check etc. You will get hands-on exposure to industry standard tools and methodologies while working alongside experienced engineers.

Job Responsibilities / Day-to-Day Activities

• Should be able to develop constraints for different timing modes like Functional, Scan shift etc
• Able to do static timing checks like check timing, update timing and able debug issues in this
• Should be able to debug Formality/Conformal logical equivalence check (LEC)
  

Qualifications & Experiences:

• B.E/B.Tech/M.Tech in Electronics, VLSI or related field.
• Strong understanding of digital logic design and timing constraints & STA.
• Understanding of Verilog
• Familiartiy with EDA tools and scripting