Analog Layout Engineer

HCL Technologies Limited; Ernakulam; On-site; INR 900,000 - 1,300,000; Full time

Job summary

HCL Technologies Limited is seeking an Analog Layout Engineer in Kerala, India to develop full-custom analog/mixed-signal layouts, collaborating with circuit designers and verification teams. You will translate schematics into silicon-ready layouts, ensuring performance, area, reliability, and manufacturability targets are met.

The role requires hands-on expertise in analog layout techniques, DRC/LVS/ERC/PEX workflows, and experience with advanced process nodes.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or related field.
• 3+ years of hands-on experience in Analog/Mixed-Signal Layout or Full-Custom IC Layout.

Responsibilities

• Develop full-custom analog and mixed-signal layouts from schematic to final layout closure.
• Work on layout of analog blocks such as PLL, DLL, ADC, DAC, LDO, Bandgap, Op-Amps, Comparators, Clocking circuits, SerDes/PHY and other custom analog IPs.
• Implement critical analog layout techniques such as device matching, symmetry, common-centroid placement, interdigitation, shielding, guard rings and dummy devices.
• Perform floorplanning, placement and routing while considering signal integrity, noise isolation, power routing and parasitic effects.
• Perform and debug DRC, LVS, ERC and antenna violations to achieve clean physical verification.
• Support parasitic extraction (PEX) and work closely with circuit designers to resolve post-layout performance issues.
• Optimize layouts for area, performance, matching, reliability and manufacturability.
• Address EM/IR, latch-up, ESD and reliability considerations, as applicable to the design.
• Collaborate closely with Analog Design Engineers to understand circuit-critical requirements and translate them into effective layout implementations.
• Participate in layout reviews and quality checks and ensure adherence to foundry and project-specific design guidelines.
• Contribute to continuous improvement of analog layout methodologies, automation and design flows.
• We're looking for engineers who have strong hand-on Analog Layout expertise, understand the relationship between circuit behavior and physical implementation, and can independently drive complex analog blocks toward DRC/LVS-clean, tapeout-ready layouts.

Skills

Cadence Virtuoso

CMOS device layout

Physical verification tools

Device matching

Common-centroid techniques

Interdigitation

Guard rings

Parasitic-aware routing

Noise isolation

Education

Bachelor's or Master's degree in Electrical/Electronics/VLSI/Microelectronics

Tools

Calibre

Virtuoso Layout Suite

Job description

About the Role

About the RoleAs an Analog Layout Engineer at HCLTech, you will be responsible for developing high-quality, full-custom layouts for complex analog and mixed-signal IPs. You will work closely with analog circuit designers and physical verification teams to translate schematics into silicon-ready layouts while meeting performance, area, reliability, and manufacturability requirements.

Responsibilities

• Develop full-custom analog and mixed-signal layouts from schematic to final layout closure.
• Work on layout of analog blocks such as PLL, DLL, ADC, DAC, LDO, Bandgap, Op-Amps, Comparators, Clocking circuits, SerDes/PHY and other custom analog IPs.
• Implement critical analog layout techniques such as device matching, symmetry, common-centroid placement, interdigitation, shielding, guard rings and dummy devices.
• Perform floorplanning, placement and routing while considering signal integrity, noise isolation, power routing and parasitic effects.
• Perform and debug DRC, LVS, ERC and antenna violations to achieve clean physical verification.
• Support parasitic extraction (PEX) and work closely with circuit designers to resolve post-layout performance issues.
• Optimize layouts for area, performance, matching, reliability and manufacturability.
• Address EM/IR, latch-up, ESD and reliability considerations, as applicable to the design.
• Collaborate closely with Analog Design Engineers to understand circuit-critical requirements and translate them into effective layout implementations.
• Participate in layout reviews and quality checks and ensure adherence to foundry and project-specific design guidelines.
• Contribute to continuous improvement of analog layout methodologies, automation and design flows.
• We're looking for engineers who have strong hand-on Analog Layout expertise, understand the relationship between circuit behavior and physical implementation, and can independently drive complex analog blocks toward DRC/LVS-clean, tapeout-ready layouts.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or related field.
• 3+ years of hands-on experience in Analog/Mixed-Signal Layout or Full-Custom IC Layout.

Required Skills

• Strong hands-on experience with Cadence Virtuoso Layout Suite or equivalent industry-standard custom layout tools.
• Strong understanding of CMOS device layout and semiconductor fundamentals.
• Hands-on experience with DRC, LVS, ERC and PEX flows using tools such as Calibre or equivalent physical verification tools.
• Strong understanding of analog layout concepts including:

Device matching and symmetry

Common-centroid techniques

Interdigitation

Guard rings and shielding

Dummy device insertion

Parasitic-aware routing

Noise and substrate isolation

• Experience taking analog blocks from schematic through layout and physical verification closure.
• Ability to interpret schematics and identify critical signal paths, matching requirements and sensitive analog nets.
• Good debugging, analytical and communication skills.

Preferred Skills

• Experience with advanced process nodes such as 28nm, 16/14nm, 7nm, 5nm or below.
• Experience with FinFET technologies.
• Exposure to high-speed interfaces such as SerDes, DDR/LPDDR, PCIe or high-speed PHYs.
• Experience with RF, high-speed, low-power or precision analog layouts.
• Exposure to top-level/block integration and layout assembly.
• Experience working with global, cross-functional semiconductor design teams.