Analog Layout Engineer | Custom Layout Engineer | Mixed Signal Layout

Acesoft Labs; Hyderabad; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Acesoft Labs in Hyderabad requires an experienced layout engineer for analog, mixed-signal and custom digital blocks with full-chip integration. You will work with Cadence VLE/VXL and Mentor Caliber DRC/LVS, perform LVS/DRC checks, and drive on-time delivery while mentoring junior designers.

Candidates should have 3–10 years of analog/custom layout experience in advanced CMOS processes and hold BE or MTech in Electronic/VLSI Engineering. Strong communication with local teams is essential.

Qualifications

• 3 to 10 years of analog/custom layout design experience in advanced CMOS processes.
• BE or MTech in Electronic/VLSI Engineering.

Responsibilities

• Design and develop analog, mixed-signal, and custom digital blocks with full-chip integration.
• Ensure layouts meet LVS/DRC/Antenna checks and provide quality documentation.
• Deliver block-level layouts on time while maintaining quality.
• Guide junior team members in sub-block layouts and review critical items.
• Communicate effectively with local engineering teams to support layout projects.
• Demonstrate problem-solving in physical verification and project milestones.

Skills

Analog layout

Mixed-signal layout

Custom digital layout

Full-chip integration

Layout verification

Mentoring juniors

Education

BE or MTech in Electronic/VLSI Engineering

Tools

Cadence VLE/VXL

Mentor Caliber DRC/LVS

Job description

Role & responsibilities

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support.

Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.

Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.

Responsible for on-time delivery of block-level layouts with acceptable quality.

Excellent problem-solving skills in physical verification of custom layout.

Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment.

Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items.

Contribute to effective project-management.

Effectively communicating with Local engineering teams to assure the success of layout project.

NOTE: custom layout or analog layout with TSMC 3nm/5nm7nm & 3+ exp (relevant) are preffered

Educational Background

• BE or MTech in Electronic/VLSI Engineering

• 3 to 10 year experience in analog/custom layout design in advanced CMOS process.