SRAM / Memory Compiler Design Engineer - 0074

Sunrise Biztech Systems; Hyderabad; On-site; INR 800,000 - 1,200,000; Part time

Job summary

Sunrise Biztech Systems Pvt. Ltd. in Hyderabad is seeking an SRAM/Memory Compiler Engineer with 2–4 years of experience.

You will read and interpret documentation, respond to end-user queries, and generate memory views for Synopsys memory compilers. The role requires familiarity with memory design flows and verification practices, including DRC/LVS. The position involves QA of released views, scripting for automation, and collaboration with the team to meet project timelines.

Qualifications

• SRAMs and memory compilers understanding and VLSI flow.
• Memory views: Verilog, timing (.lib), LEF, GDS.
• Physical design verification: DRC and LVS.
• Circuit simulations with SPICE.
• Scripting: PERL, Unix shell, Tcl, Python.
• 2–4 years of experience.

Responsibilities

• Read and understand documentation and answer end-user questions regarding Synopsys memory compilers.
• Generate compiled memory views and perform QA on those views for each released version.
• Perform program management, tracking action items and progress against due dates.

Skills

Memory compilers

Memory design flow

Verilog

SPICE simulations

Tools

Verilog

SPICE

LEF

GDS

Python

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our top leading semiconductor client. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: SRAM / Memory Compiler Engineer
Experience: 2-4 Years

Location: Hyderabad

Contract tenure: 9 Months

Responsibilities will include:

Read and understand documentation of and answer end-user question regarding Synopsys memory compilers Generate compiled memory views and perform quality assurance on those views for each released version. Perform program management, tracking action items and progress against due dates.

EXPERIENCE AND EDUCATION:

• Understanding of SRAMs and memory compilers (Synopsis Memory Compiler experience preferred) as well as VLSI design flow
• Familiarity with memory design and views of memories, e.g. Verilog, timing (.lib), LEF, GDS
• Familiarity with physical design verification, e.g. DRC and LVS
• Able to perform and interpret circuit simulations, e.g. using SPICE
• Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language.
• 2-4 years of experience