Senior Memory Design Engineer

Broadcom; Bengaluru; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Broadcom is seeking a Senior Design Engineer to contribute to the design and development of high-speed, low-power memory components, including SRAM and memory compilers, in advanced nodes. You will simulate bitcells, decoders, and control logic, and drive margin and sign-off through detailed characterization flows.

Candidates should have strong experience in Cadence/Mentor tooling, HSPICE, and scripting (Python/Perl).

Qualifications

• Expertise in high speed/low power CMOS circuit design and clocking schemes.
• Experience driving memory compiler specifications to final release.
• Strong debugging, failure analysis and silicon debug experience.

Responsibilities

• Lead design and development of Single/Multiport SRAM and register file compilers.
• Circuit design, simulation of bitcell, decoders, SAMP and control logic.
• Develop characterization flow and margin simulations for sign-off.
• Perform statistical analysis on bit-cell, sense amp and timing blocks.
• Execute design tuning, margin analysis and sign-off for yield targets.
• Conduct timing analysis and signal integrity checks on memory paths.
• Perform IR drop analysis and EM concerns in high-speed memory designs.

Skills

CMOS circuit design

Memory compilers

Power gating

Clocking schemes

Silicon debugging

Cadence/Mentor tools

HSPICE simulations

Python/Perl scripting

Layout issues analysis

Education

Masters Degree

Bachelors Degree

Tools

Cadence

Mentor Graphics

HSPICE

nWave

XARA/FinSim

Job description

Job Description:

JD for Senior Design Engineer

1. Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies
2. Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic.
3. Development of critical path and characterization flow to perform detailed margin and characterization simulations.
4. Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off
5. Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets.
6. Logic simulations and detailed timing analysis of key paths in high speed memory design.
7. Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.

Skill Sets/Prerequisites

1. Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits
2. Experience in Designing and driving one or many Memory Compilers Specifications to final release
3. Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design
4. Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing.
   5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools
5. Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc
6. Experience in Skill/Perl/Python Scripting is a strong plus
7. Experience in Understanding the layout design issues in sub nanometer regime is a must.

1. Expertise in Understanding Memory DFT is a Plus.
2. Masters Degree with 4+ Years or Bachelors Degree with 5+ years

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.