SRAM Senior / Staff / Principal – Design & Layout Engineers

NextiCron Technologies

Bengaluru

Hybrid

INR 3,500,000 - 7,000,000

Full time

2 days ago
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Job summary

NextiCron Technologies is expanding its SRAM and memory compiler development team. We seek experienced semiconductor professionals with strong memory circuit design, compiler development, and memory layout expertise.

The role involves designing SRAM/ROM/memory compilers, working on memory architecture, and performing extensive analysis. Flexible locations and full-time employment offered, with collaboration across layout and design teams.

Qualifications

  • 3–15 years hands-on SRAM, embedded memory, register file, ROM, or memory compiler work.
  • Role may be Senior, Staff, Principal, or Lead based on experience and expertise.
  • Strong memory architecture, transistor-level operation, margins, and PVT variation.
  • Experience with Liberty and Verilog memory models.
  • Knowledge of SRAM bitcell, peripheral layout, and parasitics.

Responsibilities

  • Design and develop SRAM, ROM, and register file memory compilers.
  • Work on memory architecture, read/write paths, sensing circuits, and control logic.
  • Perform functional, timing, power, yield, and PVT analyses.
  • Support memory characterization and Liberty/Verilog model generation.
  • Contribute to memory compiler architecture, validation, and automation flows.
  • Collaborate with layout engineers on bitcells, arrays, parasitics, and physical implementation.
  • Review layout-dependent effects and assist DRC, LVS, EM/IR, LEF, and GDS deliverables.
  • Provide technical guidance and support memory compiler development projects.

Skills

Memory compiler design
SRAM memory design
Memory circuit design
Verilog models
PVT variation analysis

Tools

Cadence
Synopsys
Siemens EDA/Calibre

Job description

Hiring: Senior SRAM / Memory Compiler Design & Layout Engineers

NextiCron Technologies is expanding its SRAM and memory compiler development team. We are looking for experienced semiconductor professionals with strong expertise in memory circuit design, compiler development, and a good understanding of custom memory layout.

Locations: Flexible
Employment Type: Full-time
Work Mode: Flexible, based on project requirements
Responsibilities
  • Design and develop SRAM, ROM, and register file memory compilers.
  • Work on memory architecture, read and write paths, sensing circuits, assist techniques, control logic, and design margins.
  • Perform functional, timing, power, yield, and PVT analysis.
  • Support memory characterization and the generation of Liberty and Verilog models.
  • Contribute to memory compiler architecture, validation, and automation flows.
  • Collaborate with custom layout engineers on bitcells, peripheral circuits, array integration, parasitic effects, and physical implementation.
  • Review layout-dependent effects and support DRC, LVS, EM/IR, LEF, and GDS deliverables.
  • Provide technical guidance and support the execution of memory compiler development projects.
Required Qualifications
  • 3–15 years of hands‑on experience in SRAM, embedded memory, register file, ROM, or memory compiler development.
  • The position may be offered at the Senior, Staff, Principal, or Lead level, depending on the candidate’s experience and technical expertise.
  • Strong understanding of memory architecture, transistor‑level circuit operation, design margins, and PVT variation.
  • Experience with memory characterization and deliverables such as Liberty and Verilog models.
  • Good understanding of SRAM bitcell and peripheral layout, array integration, parasitic effects, DRC, and LVS.
  • Hands‑on experience with Cadence, Synopsys, Siemens EDA/Calibre, or equivalent semiconductor design tools.
  • Experience with advanced‑node or foundry‑based memory development is preferred.
  • Direct experience in custom memory layout would be an advantage.
NOTE: This opening is specifically for professionals with relevant experience in VLSI, semiconductor memory design, custom IC layout, memory characterization, or memory compiler development.

Applications from general electrical engineering, mechanical engineering, power systems, embedded systems, PCB design, manufacturing, or unrelated software backgrounds will not be considered

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