Senior Memory Design Engineer

Broadcom Inc.; Bengaluru; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Broadcom Inc. is seeking a Senior Design Engineer in Bengaluru to lead and contribute to the design and development of high-speed memory compilers, SRAM cores, and related circuitry.

You will simulate, characterize, and optimize bitcells, decoders, and control logic, ensuring robust sign-off for yield and performance. The role requires deep CMOS expertise, scripting skills, and extensive use of Cadence/Mentor tools, HSPICE, and waveform viewers.

Qualifications

• Strong expertise in high-speed CMOS design and memory compilers.
• Experience with CAD tools for schematic/layout and verification.
• Scripting in Python or Perl is a strong plus.
• Masters with 4+ years or Bachelors with 5+ years of experience.

Responsibilities

• Design and development of single/multiport SRAM and register files.
• Circuit design and simulation of bitcells, decoders, SAMP, and control logic.
• Characterization flow development and margin analysis for sign-off.
• Timing analysis of critical paths in high-speed memory designs.
• Silicon debug and reliability analysis for yield improvements.

Skills

High-speed CMOS design

Memory compiler design

Circuit timing analysis

Scripting (Python/Perl)

Cadence/Mentor tools

HSPICE/HSIM simulations

Education

Master's degree in EE

Bachelor's degree in EE

Tools

Cadence

Mentor Graphics

HSPICE/HSIM

Xtra waveform viewers (XA, nWave)

Job description

## **Job Description:**JD for Senior Design Engineer1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies 2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic. 3) Development of critical path and characterization flow to perform detailed margin and characterization simulations. 4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off 5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets. 6) Logic simulations and detailed timing analysis of key paths in high speed memory design. 7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.Skill Sets/Prerequisites 1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits 2) Experience in Designing and driving one or many Memory Compilers Specifications to final release 3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design 4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing. 5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools 6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc 7) Experience in Skill/Perl/Python Scripting is a strong plus 8) Experience in Understanding the layout design issues in sub nanometer regime is a must. 9. Expertise in Understanding Memory DFT is a Plus. 10. Masters Degree with 4+ Years or Bachelors Degree with 5+ years