Physical Design Engineer-memory complier

Sunrise Biztech Systems; Hyderabad; On-site; INR 1,200,000 - 1,700,000; Full time

Job summary

Sunrise Biztech Systems in Hyderabad seeks a memory design engineer with 5+ years of experience in physical design and VLSI. You will work on memory compiler flows, read documentation, and generate memory views for multiple projects.

You will need strong scripting skills (Perl, Unix shell, Tcl, Python) and knowledge of SRAMs, Verilog, timing/.lib, LEF, and GDS. This onsite role requires excellent communication and collaboration across a global team.

Qualifications

• 5+ years of experience in physical design, VLSI, and memory compiler flows
• Proficient in PERL, Unix shell, Tcl, Python
• Knowledge of SRAMs and memory compiler concepts
• Understanding of Verilog, timing (.lib), LEF, and GDSI

Responsibilities

• Read and understand documentation of Synopsys memory compilers and answer end-user questions
• Generate compiled memory views and perform QA on released versions
• Perform program management and track items against due dates
• Support multiple projects in a globally distributed team

Skills

Physical design

VLSI

Memory technologies

Synthesis flows

PERL scripting

Unix shell

Tcl

Python

Communication skills

Education

B.E./B.Tech

M.E./M.Tech

Tools

Synopsys memory compiler

Job description

Description: Location: Hyderabad
Work Mode: Onsite(all 5 days)
Round of interviews: 2
R1: F2F
R2: F2F(Both interviews will happen on the same day)
Exp: 5+ years
Education: B.E/B.tech/M.E/M.tech

Skills: 5+ years of exp in 5 + years of experience in Physical design engineer, VLSI, FCFCP prior supporting experience in AMD TB flows preferably
Good knowledge on relevant script languages in PERL, Unix shell, Tcl, Python etc

• Communication skills

JD: Must solid experience with memory technologies, and a desire to develop broader exposure to their downstream use in a dynamic, cutting edge VLSI Synthesis environment. This role will provide key support for multiple projects in a globally distributed team.

• Read and understand documentation of and answer end-user question regarding Synopsys memory compilers.
• Generate compiled memory views and perform quality assurance on those views for each released version.
• Perform program management, tracking action items and progress against due dates.

• Understanding of SRAMs and memory compilers (Synopsis Memory Compiler experience preferred) as well as VLSI design flow
• Familiarity with memory design and views of memories, e.g. Verilog, timing (.lib), LEF, GDS
• Familiarity with physical design verification, e.g. DRC and LVS
• Able to perform and interpret circuit simulations, e.g. using SPICE
• Ability to execute and modify scripts in PERL, Unix shell, Tcl, Python or related language

6 to 9 years of experience