Memory Design Engineer

Broadcom Inc.; Bengaluru; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

Broadcom Inc. in Bengaluru is seeking a Memory Design Engineer to contribute to the design and development of single and multiport SRAM and memory compilers across advanced nodes.

You will work on circuit design, timing, and simulations, including bitcell, decoders, and control logic, with a focus on yield, performance, and reliability.

Qualifications

• Experience in high-speed, low-power CMOS circuit design.
• Proven track record in designing memory compilers.
• Deep knowledge of split-rail and power gating architectures.
• Hands-on silicon debugging and failure analysis experience.
• Proficient with Cadence/Mentor schematic/layout tools and circuit simulation.

Responsibilities

• Lead design and development of SRAM and memory compilers.
• Perform timing, margin, and yield sign-off analyses.
• Conduct SI/IR drop analysis and EM integrity checks.
• Develop characterization flows and statistical analyses for targets.

Skills

CMOS circuit design

Memory compilers

Power gating architecture

Silicon debugging

Cadence/Mentor tools

Circuit simulation

Perl/Python scripting

Sub-nanometer layout understanding

Memory DFT

Education

Master's or Bachelor's degree in ECE/EE or related field

Tools

HSPICE

HSIM

XA

FinSim

XARA

nWave

Waveform viewer tools

Job description

## Memory Design EngineerApply: IND-Bangalore Electronic City - S1: Full time: Posted Yesterday: R027064**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **Job Description:**JD for Memory Design Engineer1) Contribute/Lead towards Design and Development of Single/Multiport SRAM, Register file compilers in 28nm/16FF/7FF/5FF Technologies 2) Circuit design/simulation of key components such as bitcell, WL decoder, SAMP, Column decoder and control logic. 3) Development of critical path and characterization flow to perform detailed margin and characterization simulations. 4) Statistical Analysis of Bit-Cell and Sense Amplifier and Self Time Blocks for Compiler Target yield Sign-Off 5) Design Tuning, Margin Analysis and Sign-Off for Complete Compiler to meet Yield and Performance targets. 6) Logic simulations and detailed timing analysis of key paths in high speed memory design. 7) Signal-Integrity (EM) and Power-Integrity (IR drop) analysis and design.Skill Sets/Prerequisites 1) Expertise of high speed/low power CMOS circuit design, clocking scheme, Static and dynamic logic circuits 2) Experience in Designing and driving one or many Memory Compilers Specifications to final release 3) Deep expertise in Understanding and Developing Split rail, Power gating Architecture and circuit design 4) Hands on Experience on Silicon Debug/Diagnose the failures. Deep expertise on Silicon Failures, Analysis and fixing. 5 Complete hands on experience in using Cadence/Mentor schematic/layout editor tools 6) Complete hands on experience with Circuit simulation, MC analysis and waveform viewer tools such as HSPICE, HSIM, XA, FinSim, XARA, nWave, waveform viewer etc 7) Experience in Skill/Perl/Python Scripting is a strong plus 8) Experience in Understanding the layout design issues in sub nanometer regime is a must. 9. Expertise in Understanding Memory DFT is a Plus. 10. Masters Degree with 2+ Years or Bachelors Degree with 3+ years