Memory Circuit Design Engineer

UST; Bengaluru; On-site; INR 1,600,000 - 2,200,000; Full time

Job summary

UST is seeking an experienced SRAM compiler design engineer for Bengaluru. The candidate should hold an MTech or BTech in Electronics & Communication or a related field and bring 4+ years of hands-on SRAM compiler design experience.

The role involves characterization, design verifications using True spice and fast spice, and executing day-to-day tasks under supervision from the Project Leader/Design Architect.

Qualifications

• MTech/BTech degree in Electronics & Communication or related field is required.
• At least 4+ years of SRAM compiler design experience.
• Hands-on experience with characterization and spice-based verifications.

Responsibilities

• Execute day-to-day tasks under supervision from Project Leader/Design Architect.
• Contribute to timing, power, and leakage analyses for SRAM blocks.
• Support design verifications using True spice and fast spice tools.

Skills

Characterization

Spice verification

LVF analysis

CPTs

FCTS

Read/Write selftime

Power sequencing

Bitcell design

Memory blocks design

Education

MTech/BTech in Electronics & Communication or related field

Tools

True spice

Fast spice

Job description

This role should have a MTech/BTech degree in Electronics & Communication or related field with at least 4+ years of SRAM compiler designexperience. The person should have hands on experience in Characterization, design verifications using True spice and fast spice. Must be able to execute day-to-day jobs with supervision from Project Leader/Design Architect.

Responsibilities

Qualification

• MTech/BTech degree in Electronics & Communication or related field
• At least 4+ years of SRAM compiler designexperience

Required Skills

• Hands on experience in Characterization
• Design verifications using True spice and fast spice
• Must be able to execute day-to-day jobs with supervision from Project Leader/Design Architect
• Detailed Skill Set:
• Bitcell Design
• Design of simpler memory blocks (decoding, rowdec, SA, IO block w/o RA, WA)
• Design of complex blocks like RA, WA, Rd selftime and write selftime
• Read/Write Selftime Analysis
• Functional/Power Marginality analysis
• Latch analysis
• ESPCV
• Power ON and power sequencing checks
• Timing, power, leak etc. setups(definitions, stimuli, MCF etc.)
• Timing, power, leak etc. verification (new addition)
• LVF analysis and implementation
• Critical Path Tight Stimuli (CPTS)
• Full Cut Tight Stimuli (FCTS)
• FC power, timing, power, leak and comparison with CP
• Decoupling CAP

Preferred Skills

• Extraction, IR/EM analysis, PERC etc. – Nice to have