Sr Principal Design Engineer

Cadence; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Cadence in Bengaluru seeks a seasoned VLSI verification engineer with 12-14 years in VLSI, expert in Verilog and HVL with UVM-based methodologies. You will contribute to delivering robust verification environments and complex test-bench components.

You will lead independent delivery, develop assertions, constraints, and coverage, and script in Perl/Tcl to automate flows while mentoring teams.

Qualifications

• 12-14 years of work experience in VLSI domain.
• Master’s or Bachelor’s degree in engineering.
• Proficient in Verilog and HVL (SV, Specman e) with UVM/OVM/eRM.
• Experience in assertions development/closure, constraint randomization, and coverage (functional and code).
• Test-bench development and RTL/GLS sim debugging.
• Ability to manage project schedule and delivery independently.
• Proficiency in Perl/Tcl scripting and automation.

Responsibilities

• Develop and maintain robust verification environments and test benches.
• Drive assertion development, coverage closure, and constrained randomness.
• Coordinate delivery timelines and collaborate with cross-functional teams.

Skills

Verilog

HVL SV Specman

UVM/OVM/eRM

Assertions development

Constraint randomization

Functional and code coverage

Test-bench development

RTL debugging

GLS debugging

Project management

Perl scripting

Tcl scripting

Education

Master's degree in Engineering

Bachelor's degree in Engineering

Tools

Perl

Tcl

Job description

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering. Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology. Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification. Expertise in test-bench development. Strong RTL and GLS (w/ or w/o SDF) sim debug skills. Should be able to manage project schedule and delivery independently.

Should be good in Perl/Tcl scripting and automation.

We’re doing work that matters. Help us solve what others can’t.

Requirements: