DV Engineer (Design Verification Engineer)

PQAngels Tech; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

PQAngels Tech in Bengaluru seeks a Design Verification Engineer with strong SystemVerilog and UVM expertise to verify complex SoC/IP designs. You will build verification environments, write test plans, and debug RTL issues in close collaboration with RTL designers.

The role involves regression and coverage closure, constraint random verification, and scripting support using Perl/Python/Shell. Candidates should have hands-on experience in ASIC/SoC verification flows and debugging with simulators.

Qualifications

• Strong SystemVerilog and UVM knowledge
• Experience in ASIC/SoC verification flow
• Debugging skills using simulators
• Perl/Python/Shell scripting knowledge preferred

Responsibilities

• Functional and code coverage analysis
• Constraint random verification
• Automation and scripting support

Skills

SystemVerilog/UVM knowledge

ASIC/SoC verification flow

Debugging with simulators

Perl/Python/Shell scripting

Job description

Department

VLSI

Location

About the Role

We are seeking a Design Verification Engineer with strong knowledge in SystemVerilog, UVM, and functional verification methodologies for complex SoC/IP verification projects.

Job Description

• Develop verification environments using SystemVerilog/UVM


• Create test plans, testcases, assertions, and coverage models


• Debug RTL and verification issues


• Work closely with RTL designers and architects


• Perform regression and coverage closure

Responsibilities

• Functional and code coverage analysis


• Constraint random verification


• Automation and scripting support

Required Skills

• Strong SystemVerilog and UVM knowledge


• Experience in ASIC/SoC verification flow


• Debugging skills using simulators


• Perl/Python/Shell scripting knowledge preferred

We believe in equality of opportunity. To live. To succeed. To grow. To be more than.